Automatic Placement Research Articles

A Study on Application of Genetic Algorithm to Automatic Placement of Parts on Printed Circuit Boards.

For computer aided design (CAD)/design automation (DA) for printed circuit board (PCB), automatic placement of parts has been strongly needed. It is, however, very difficult to realize the automatic placement, since the parts have wide variety in size and these parts should be placed under various constraints.This paper studies a method of placement on the PCB using genetic algorithm (GA). This paper also studies an application of a new representing method for maintaining diversity of chromosomes to the GA. Simulations are done to show the feasibility of the new automatic placement method. A chromosome is converted into multiple phenotypes by the methods.

Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New analytical procedure for automatic cell placement in gate-arrays

A fully automated constructive global placement method based on analytical function minimisation is described. It is meant to be applied to the gate-array placement problem, which is known to be a most restrictive one. A penalty function approach is used to convert the problem into an unconstrained optimisation. The objective function is constructed of two parts: the first one, reflecting the attraction criterion, generates the so-called 'relative placement', while the second one assembles the repulsion requirements (in which the essential geometric requirements are incorporated), and generates the so-called 'geometric placement' or 'final placement'. The geometric requirements are introduced sequentially so that a strategy is proposed to enable the final solution (which becomes suboptimal in the sense that a longer interconnection length is obtained) to be kept as near as possible to the relative one. No convergence problems are encountered even for complex examples. Among the introduced penalty functions the most important one is the nonoverlapping penalty function. Here, a new, good approximation of the rectangular module shape is introduced enabling analytical definition of the constraints. It was recognised that, for complex placement problems, the nonoverlapping penalty was not strong enough to ensure nonoverlapping. Hence a new repulsive penalty is introduced which takes into account the module dimensions. Fully automatic row assignment of the modules is ensured by another new penalty. The gate assignment is performed automatically but, in order to avoid integer programming, it is performed as a separate post-processing phase. Examples of complex design were produced utilising 90% of the gate-array central area.

An experimental comparison of systematic placement procedures for facility layout design

Abstract A comparison of alternative procedures for automatic placement of facilities in a layout is presented. Various placement procedures are reviewed, incorporated in an existing ‘construction’ type heuristic and evaluated in terms of placement computation time, satisfaction of goals expressed using linguistic patterns, fulfilment of desired adjacency of facilities and regularity of shapes of facilities in resulting layouts. An experiment illustrates the application of various placement procedures fora set of randomly generated and known layout problems to compare the performance of alternative placement procedures.

Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology

The performance of multilevel logic minimization tools for a lookup-table-based field-programmable gate array (FPGA) technology was examined. The experiments used the university tools, misII for combinational logic minimization and mustang for state assignments, and the industrial tools xnfmap for technology mapping and apr for automatic placement and routing. The quality of the multilevel logic minimization tools was measured by the number of routed configurable logic blocks (CLBs) in the FPGA realization. A linear relationship between the number of literals and the number of routed CLBs was found. In all 34 MCNC-89 benchmark finite state machines, one-hot state assignment resulted in substantially fewer CLBs than any other state encoding methods available in mustang. A delay model that provides routing delay prediction based on fan-out is presented and used to estimate the delays of the FPGA implementation of logic expressions prior to technology mapping, place, and route.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Auto-placement of semi-graphic flow diagrams

Semi-graphic flow diagrams on instrument panels are useful in the operation of a continuous production plant. The design of such diagrams is a time-consuming job and is highly reliant on engineers' expertise. With the assistance of computer tools, the design process can be simplified as well as the quality improved. In developing an automatic design system for semi-graphic flow diagrams, the design procedure is divided into two phases, placement and routing. This paper includes the related algorithms for the automatic placement of symbolic expressions of plant equipment onto drafting paper. The placement procedure described here follows the sequence of data processing, initial placement, balancing placement, and sequential modification. An example product generated by the design system is also included.

FUZZY LOGIC FOR STANDARD CELL PLACEMENT

Improved manufacturing processes and techniques have increased the level of integration and complexity of the ubiquitous silicon chip. But as design complexity grows, physical design automation becomes indispensable. At present a variety of tools are available to assist the designer in the various phases of circuit design. Tools for automatic placement of VLSI cells, in particular, have received much attention, because good placement is a key factor in achieving the demanded performance levels. In this paper, we present a new technique based on fuzzy logic for the placement of double-entry standard cells. Fuzzy logic offers a better alternative for handling uncertainty, and it models the human operator rather than the operation. Simulation results for the placement of nine test circuits are presented and compared with those of two other techniques.

Analysis of alternative rework strategies for printed wiring assembly manufacturing systems : Morris Driels and Major John S. Klegka. IEEE Trans. Compon. Hybrids mfg Technol.14(3), 637 (1991)

This paper presents a model for predicting the cost of test, diagnosis, and rework activities in the manufacture of printed wiring assemblies (PWA's). Rework is defined as all actions taken to correct or improve the basic assembly process. These actions may include those of inspectors and solder touchup technicians who do not add value to the PWA, but whose actions are required in order to produce acceptable yields from the manufacturing process. Two alternative rework strategies for contemporary PWA manufacturing systems are presented: terminal rework and distributed rework. Rework may occur after all assembly operations have been accomplished (terminal rework) or it may be distributed throughout the assembly process. This paper allalyzes the economic basis for deciding between the two rework strategies. The paper assumes that the only reason for utilizing distributed rework is to reduce the cost of producing acceptable PWA's, otherwise the cost of the distributed rework effort cannot be justified. The paper presents a model of each rework strategy. The effect of each strategy upon first pass yield (FPY) of the manufacturing process is discussed. The effect on FPY is then used to evaluate the economic benefit of each rework strategy as an aid in deciding which strategy to use. The increase in FPY needed to justify distributed rework is calculated. I. PWA MANUFACTURING SYSTEMS WIDE variety of printed wiring assembly (PWA) manA ufacturing systems may be observed throughout the industry. These systems have been developed to operate efficiently in specific areas of the PWA manufacturing environment as determined by factors such as technology, production volume, design complexity, component types, and product life span. In the area of surface mount technology (SMT), for example, considerable standardization has been achieved in interconnect methods, component shapes and packaging, and substrate design. As a result, a wide variety of SMT products are manufactured using very similar assembly systems. In order to accurately predict the costs associated with operating these systems, they must be modeled on a detailed basis. To obtain the needed detail, models have been developed in which the total system is decomposed into individual modules. The individual modules are analyzed to model the cost and performance of each station [l], [2 ] . Manuscript received May 14, 1990; revised April 10, 1991. M. Driels is with the Department of Mechanical Engineering, Naval Major J. S. Klegka is with the Department of Civil and Mechanical IEEE Log Number 9101464. Postgraduate School, Monterey, CA 93943. Engineering, United States Military Academy, West Point, NY 10996. Ill 11111 I11111 I lllllllllllrl 631 A PWA manufacturing system usually consists of a series of automated and manual assembly and process stations. The stations may be connected by an automatic or manual transfer device which moves the partially completed PWA's through the system. Each PWA follows a relatively fixed path through the manufacturing system. A typical assembly system consists of a solder paste dispenser, one or more automatic component placement machines, one or more manual inspection and placement stations, a solder reflow station, a cleaning station, and a test, diagnosis, and rework station [8], [9],

The pseudoexhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Automatic resistor-generation and thick film circuit layout using the Magic layout editor

Abstract A technology file for the Magic layout editor has been developed to show the possibility of a design route which uses a CAD package not intended for hybrids, and as such it is considered to be a low cost approach to thick film CAD. Layout with design rule checking of multilayer hybrid circuits may be performed, consisting of two (or more) different metallization patterns with the possibility of using up to eight different resistor pastes, dielectrics, protective coating and solder paste. The thick film technology described is not meant to be indicative of good industrial practice, since the intention is to show how the technology file may be altered. The alterations performed provide for automatic resistor generation, device placement and automatic routing techniques in thick film circuits. Also, in single-layer technology, dielectric tiles are automatically created at metal crossings when an electric contact is not desired.

Hemoptysis Complicating AICD Patch Placement Controlled by Temporary Selective Bronchial Balloon Occlusion

This is the first reported case of an automatic implantable cardioverter-defibrillator patch placement complicated by hemoptysis. It is also notable because the patient's massive hemoptysis was managed by a balloon occlusion catheter inserted into the segmental bronchus through the endotracheal tube with fluoroscopic guidance.

Mixed venous oximetry during automatic implantable cardioverter-defibrillator placement

Mixed venous oxygen saturation (Sv̄0 2) monitoring was used to assess tissue and circulatory recovery following induced ventricular tachycardia or fibrillation in 17 patients undergoing surgery for automatic implantable cardioverter-defibrillator (AICD) placement. Return of systemic arterial pressure conventionally determines adequate recovery. The duration of circulatory arrest during defibrillator threshold (DFT) testing, measured from the moment of absent phasic pressure at the radial artery until its return, was 18 ± 18 seconds (mean ± SD, n = 118 episodes). The absolute decrease in Sv̄0 2 from baseline to nadir for these 118 episodes was 14% ± 6% absolute, and correlated well with the duration of circulatory arrest ( r = 0.757, P = 0.0001). The time from onset of phasic arterial blood pressure to the nadir of Sv̄0 2, available for 46 episodes, was 28 ± 14 seconds, and did not correlate with the duration of arrest. The time from onset of phasic pressure to the return of Sv̄O 2 to within 1 % (absolute) of baseline saturation, available for 84 episodes, was 52 ± 32 seconds and, in the aggregate, correlated poorly ( r = 0.401) with duration of arrest. Simultaneous recording of arterial pressure and Sv̄0 2 (n = 41) showed that arterial recovery (6 ± 3 seconds) occurred long before Sv̄0 2 recovery (48 ± 16 seconds, P = 0.0001). The authors interpret these data as showing that mixed venous oximetry, compared to arterial blood pressure, provides a more sensitive indicator of tissue recovery following periods of circulatory arrest during DFT testing of AICDs.

A Technique for Intraoperative Arrhythmia Induction during Automatic Implantable Defibrillator Placement

In 14 patients (12 men, 2 women, mean age 51 +/- 4 years) we evaluated a new technique for intraoperative arrhythmia induction during Ventak 1550 automatic implantable cardioverter defibrillator (AICD), pulse generator placement. At the time of surgery (nine new implants, five pulse generator replacements), when the AICD pulse generator is in its final configuration with the rate sensing and patch electrodes leads inserted into the header, a #2 hex wrench was inserted into each of the rate sensing lead set screw sites. The alligator clips of a temporary pacing cable were placed on each of the hex wrenches and the remainder of the cable passed off field for attachment to a programmed stimulator or AC fibrillator. In all 14 patients, the clinical arrhythmia was induced at least twice (ventricular tachycardia in eight patients, ventricular fibrillation in six patients). No difficulties with arrhythmia induction or AICD sensing as discharge were encountered. We conclude that this technique is both a safe and effective means of intraoperative arrhythmia induction during placement or replacement in the Ventak AICD 1550 and 1600 series pulse generators.

Integration and Application of Vision Systems in SMD Automatic Placement Machines

The mechanical design of the automatic placement machine and the integrated application of different tools dictate the result of the placement process. The placement accuracy of the system is a decisive factor for the quality and cost of the printed circuit board. Vision systems have become indispensable in today's SMD placement technology.

Marker-making using automatic placement of irregular shapes for the garment industry

The CORTE system, integrating CAD and production management functions, was developed for use in the Portuguese garment industry. This paper describes the sliding algorithm for interactive placement of irregular shapes used in the GIZ graphic editor and a heuristical approach which uses that algorithm for fully automatic placement.

Computational geometric methods in volumetric intersection for 3D reconstruction

Generation and analysis of 3D models is an important task that enables automatic inspection, placement, and manipulation of physical objects by robotic systems. This work presents a new approach to the generation of 3D models of arbitrarily shaped physical objects. The models are generated from intensity images obtained from known view positions. The objects are modelled by contours on successive parallel planes. The model becomes more refined as more images are used. The contour model supports the ability to generate the surface of an object by means of tessellation. We have developed a model that supports efficient intersection, not only to perform reconstruction, but also to support inclusion testing and collision detection. We have implemented this algorithm using images of real objects. The algorithm's time complexity is linear with the number of views used and with the number of objects reconstructed. The resolution of the algorithm in reconstructing the contours is limited only by machine precision constraints. This is because the intersection points of the contours are determined analytically, by solving sets of simultaneous equations, which describe the line segments that compose the contours.

バスに着目した自動配置システム

バスに着目した自動配置システム

Map data processing in geographic information systems

An overview of geographic information systems (GISs) is given, covering data collection, applications, organization, and data models. Recent trends in map data processing are examined, namely, automatic name placement, map generalization, an automatic digitizer and expert system for land-use analysis, a map oriented system for urban planning, and a knowledge-based GIS. Techniques for extracting information from paper-based images are discussed, and some experimental results are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simple but effective techniques for NUMA memory management

Multiprocessors with non-uniform memory access times introduce the problem of placing data near the processes that use them, in order to improve performance. We have implemented an automatic page placement strategy in the Mach operating system on the IBM ACE multiprocessor workstation. Our experience indicates that even very simple automatic strategies can produce nearly optimal page placement. It also suggests that the greatest leverage for further performance improvement lies in reducing false sharing , which occurs when the same page contains objects that would best be placed in different memories.

Optimization of the movements of a component placement machine

The efficient operation of an automatic electronic component placement machine (Panasert RH) is considered. The machine inserts electronic components into predefined places on a printed circuit board. The components are supplied from a set of feeders each containing a sequence of identical components. We treat the problem as two different sequencing problems. The optimal insertion sequence for a fixed feeder setting is obtained by considering the problem as a three-dimensional asymmetric traveling salesman problem. The optimal permutation of the components in the feeders for a fixed insertion sequence can be formulated as a quadratic assignment problem. The overall problem is solved heuristically and this approach brings suboptimal, but in practice good enough component insertion sequences and feeder permutations.