Automatic Gain Control Amplifier Research Articles

A Linear-in-Decibel Automatic Gain Control Amplifier With Dual Mode Continuous Gain Tuning

A reconfigurable fully integrated automatic gain control (AGC) amplifier is presented which is based on a dual mode continuous gain adjustment variable-gain amplifier (VGA). The VGA is realized based on the current-steering structure, achieving a linear-in-dB gain tuned by AGC’s feedback voltage. A current division active load is proposed, which provides additional gain control range and realizes gain robustness to process and supply variations without extra calibration. Simulated with Cadence IC, the maximum gain variations due to process and supply variations are 3.5 dB and 2.6 dB, respectively. By using dual mode gain tuning technique, the VGA achieves a total gain range of 68.2 dB. Both bandwidth and gain of the VGA are adjusted independently. The AGC is realized in UMC 55-nm CMOS technology with 0.026 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. With the current division ratio K of 0.5, the proposed VGA achieves a linear-in-dB gain of 42.2 dB ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 30.0 to 12.2 dB) with less than 0.79 dB error. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3 dB bandwidth can be adjusted from 80 MHz to 140 MHz and is insensitive to gain variations. The power dissipation is from 2.9 mW to 4.5 mW. This design features bandwidth scalability and the gain independent of bandwidth to achieve various applications.

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as fT-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 231–1 with a bit-error rate (BER) of 10−12 at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mVpp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications

This paper reports a wideband inductorless automatic gain control (AGC) amplifier for wireline applications. To realize a dB-linear AGC range, a pseudo-folded Gilbert cell driven by a single-branch negative exponential generator (NEG) is proposed as the core variable-gain amplifier. The NEG features a composite of dual Taylor series to extend the AGC approximation range without sacrificing the precision. Fabricated in 65-nm CMOS, the AGC amplifier occupies a tiny die area of 0.045 mm2 and consumes 28 mW at 1.2 V. Measured over a dB-linear gain range of ~40 dB, < ± 1 dB gain error is achieved and the 3-dB bandwidth stays roughly constant at 7 GHz. For the closed-loop AGC measurement, the input dynamic range is ~40 dB (10 mVpp to 1 Vpp) for a BER <10−12 under a 27 − 1 PRBS data at 10 Gb/s. The achieved figure-of-merit (FOM) of 2.8 pJ/bit compares favorably with state-of-the-art.

Low-cost bidirectional hybrid fiber-visible laser light communication system based on carrier-less amplitude phase modulation

We propose a bidirectional hybrid fiber-visible laser light communication (fiber-VLC) system. To reduce the cost of the system, the cheap and easy integration red vertical cavity surface emitting lasers, low-complexity carrier-less amplitude phase modulation format, and wavelength reuse technique are utilized. Meanwhile, the automatic gain control amplifier voltage and bias voltage for downlink and uplink are optimized. The simulation results show that, by using the proposed system, the bit error rate of 3.8×10−3 can be achieved for 16-Gbps CAP signal after 30-km standard single mode fiber and 8-m VLC bidirectional transmission. Therefore, it indicates the feasibility and potential of proposed system for indoor access network.

A CMOS low power fast-settling AGC amplifier based on integrated RSSI

This paper presents a low power CMOS feedforward automatic gain control (AGC) amplifier based on an integrated received signal strength indicator (RSSI) with process-variation tolerance. Low ripple high dynamic RSSI and fast settling AGC are both achieved with a power-efficient implementation. Raised feedforward AGC amplifier also gets superior linearity to cascade ones due to its high dynamic range detection to input signals. No external component is needed and this design was fabricated in 0.18 μm CMOS process. The measurement results show that RSSI gains at least 60-dB log-linear range and the AGC convergence time is less than 7.8-μs for a 2 MHz signal. It draws 1.1 mA from a 1.5 V supply and obtains ?52-dB THD with 0.7 Vpp output voltage.

A Zero-Pole Reposition Based, 0.95-mW, 68-dB, Linear-in-dB, Constant-Bandwidth Variable Gain Amplifier

A variable-gain amplifier with very low power consumption and wide tuning range is presented. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by simulation in TSMC 0.18-μm N-well CMOS fabrication process. Owing to the novel zero-pole repositioning technique, the proposed circuit demonstrates very high frequency bandwidth of 79 MHz while drawing only 0.52 mA from 1.8 V power supply. The interesting results such as a very small core area of about 0.0025 mm2 as well as a wide linear-in-dB and constant-bandwidth tuning range of 68.2 dB along with a very low power consumption of 0.95 mW are achieved utilizing standard CMOS technology. The stability of the proposed VGA is verified through transient sinusoidal response analysis. Full process, voltage and temperature (PVT) variation analysis of the circuit is also investigated through Monte Carlo and corner case analysis in order to approve the robustness of the structure. Monte Carlo simulations show standard deviation values of 4.6 dB and 78.3 MHz in gain and gain-bandwidth product, respectively. These results show that our zero-pole repositioning method would lend itself well for use in low-power and high-frequency applications, especially in high-speed automatic gain control amplifiers.

GLRT Approach for Performance Improvement in Practical Burst Packet Acquisition with AGC Amplifier

For code-aided burst packet acquisition, the extensively used square-law cross-correlation noncoherent (CCN) detector is generally studied under a fixed-gain (FG) amplifier model. However, in practical communication systems an automatic-gain-control (AGC) amplifier is usually employed. In such a case CCN will significantly deteriorate, because the amplification of noise in hypothesis $${\mathcal{H }_0}$$ H 0 is larger than that of noisy signals in hypothesis $${\mathcal{H }_1}$$ H 1 . To improve detection performance, the generalized likelihood ratio test (GLRT) approach is adopted. Closed-form expressions of false alarm probability (FAP) and detection probability (DP) are derived for CCN and GLRT in both FG and AGC cases. Based on these expressions, GLRT is compared with CCN in terms of both performance and implementation complexity. Results show that although GLRT reveals a slightly poorer performance than CCN in an ideal case that an FG amplifier is used, it achieves a significant and increasing performance superiority over CCN in a practical case that AGC is exploited with an affordable extra hardware cost.

A 5-Gb/s Automatic Gain Control Amplifier With Temperature Compensation

This paper presents an automatic gain control (AGC) amplifier with temperature compensation for high-speed applications. The proposed AGC consists of a folded Gilbert variable gain amplifier (VGA), a dc offset canceller, inductorless post amplifiers, a linear open-loop peak detector (PD), an integrator, a symmetrical exponential voltage generator, and a compensation block for temperature stability. The novel temperature compensation scheme ensures the AGC stability and accuracy over <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 20 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,^{\circ}$</tex></formula> C–200 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,^{\circ}$</tex></formula> C by predicting the integrator biasing voltage based on the crucial blocks duplication technique. The proposed linear open loop PD combined with the linear-in-dB VGA manages the dB-linear error of less than 0.3 dB for the received signal strength indication (RSSI). The AGC chip is fabricated using a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m SiGe BiCMOS technology. Consuming a power of 72 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$~$</tex> </formula> mW from a 1.2-V supply voltage, the fabricated circuit exhibits a voltage gain of 40 dB and a 3-dB bandwidth of 7.5 GHz. With a 2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{15}-$</tex></formula> 1 pseudo-random bit sequence at 5-Gb/s, the measured peak-to-peak jitter is less than 40 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox {ps}}_{\rm pp}$</tex></formula> across the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 20 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,^{\circ}$</tex></formula> C–200 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,^{\circ}$</tex></formula> C temperature range. The low linear-in-dB error and the wide operating temperature range achieving the high-speed data input signal indicate the suitability of the proposed techniques for high-speed AGC amplifiers.

광대역 멀티미디어 시스템을 위한 다채널 중간 주파수 송수신기 설계 및 성능 분석

본 논문에서는 초고속 광대역 무선 멀티미디어 서비스를 양방향으로 제공하는 시스템을 위한 다 채널 중간주파수 변환 모듈을 설계하고 성능을 분석하였다. 먼저 송수신기를 구성하는 각 부분에 대한 기본적인 이론을 소개하고 이를 바탕으로 송수신부를 설계하고 각 모듈별로 무 변조, 변조시의 특성 및 광 대역 다 채널 신호의 발생과정에서의 채널에 따른 특성을 시간 및 주파수 영역에서 측정하였다. 송수신부의 국부 발진 신호의 위상잡음 특성은 70dBc/kHz 이하로 특성이 우수하다. 대역내 주파수 특성은 송수신 특성이 평탄하게 측정되었다. 한편 송수신기의 자동이득조절 기능은 상당히 우수한 것으로 나타났다. 또한 이웃채널 간섭의 영향과 스퓨리어스 방사에 대한 성능분석도 하였다. In this paper, the multichannel intermediate frequency transceiver for broadband multimedia system is designed and the experimental results are analyzed. Basic elements of the transceiver such as frequency synthesizer, amplifier, mixer, automatic gain control amplifier are introduced. The analysis technique described here applies not only to amplifier but also to any other nonlinear components such as mixers and frequency doubler. Through the investigation of the power spectrum density of the transmitted signal, the phase noise of the local oscillator is evaluated below 70 dBc/kHz. The frequency characteristics of the modulated signal is flat within the system bandwidth. Also the effects of adjacent channel interference and supurious emission are analyzed. And the function of automatic gain control amplifier is well operated.

Effects of optical communication receiver circuits on Q and BER estimation accuracy

Q factor and bit error rate (BER) estimation based on synchronous and asynchronous sampling have been established as an important method for performance monitoring in optical networks. This study presents a simple model that estimates Q and BER from experimental data using curve fitting under the Gaussian assumption. The model improves estimation accuracy by optimising the receiver analog front end and correcting for sampling errors. The effects of front-end analog amplifiers on the sampling method accuracy have been investigated experimentally by using different optical receivers and post-amplifiers. The results show that the estimated Q and BER track the experimental values over a wide power range. In addition, post-amplifiers operating in the linear region with carefully optimised gain result in a more accurate Q and BER compared to automatic gain control amplifiers.

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications

This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV p–p with a BER of 10 −12 at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV p–p to 800 mV p–p, indicating a BER of 10 −12. The chip core area is 0.3 × 0.3 mm 2 and it consumes 58 mW with a single supply voltage of 1.8 V.

Wide Band Howland Bipolar Current Source using AGC Amplifier

Electrical impedance tomography (EIT) is a promising technique for imaging the conductivity distribution within the body from voltage surface measurements. The measuring precision is very important, where inaccuracies from the current source generate distortions in the images. These are particularly caused by stray capacitances which reduce the frequency response of the instrumentation. This paper investigates the performance of a bipolar current source attached to a multiplexer using an Automatic Gain Control (AGC) Amplifier circuit. Output current measurements were made in the frequency range 100 Hz to 1 MHz and also output impedance at 100 kHz, both with and without the AGC Amplifier circuit. The results showed a constant output current with a maximum error of ±2% when using the AGC Amplifier circuit whereas 300% not using it. Also, the output impedance was approximately 10.4 and 1.2 M? with and without using the AGC Amplifier circuit, respectively. It can be concluded that the AGC Amplifier circuit may increase significantly the precision of the current measurements and may improve the image quality in EIT systems.

A 0.18-$\mu{\hbox {m}}$ CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.

Wide dynamic range variable-gain amplifier based on new approximated exponential equation

A new approximated exponential equation is proposed, which offers a wide decibel linear range for use in many applications such as exponential converters, log-domain filters, variable gain amplifiers (VGAs), automatic gain control amplifiers, etc. The proposed equation is implemented into a circuit as a two-stage VGA, which is fabricated in 0.18 µm CMOS technology and offers a gain range of 90 dB (−54–36 dB) and about 82 dB with linearity error of less than ±1 dB. The 3 dB bandwidth is 50 MHz at a maximum gain of 36 dB and P1 dB is from −40 to −17 dBm. The power dissipation is 3.7 mA from a 1.8 V supply. The chip, excluding bond pads, occupies 0.34 mm2.

Jitter considerations in the design of a 10-Gb/s automatic gain control amplifier

The effects of noise on random jitter in multistage broad-band amplifiers are analyzed. Limiting amplifiers are compared to automatic gain control (AGC) amplifiers with different gain profiles. Results are presented for a 10-Gb/s AGC amplifier implemented in an SiGe process with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 45 GHz. Active peaking techniques were used to achieve a maximum gain of 48 dB with 7.8 GHz of bandwidth. The amplifier demonstrates low jitter and less than 0.5 dB of peak-to-peak output amplitude variation over a 50-dB input amplitude range. It consumes 30 mW of power from a 3.3-V supply. The amplifier core occupies 0.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and requires no external components

Development of practical surface acoustic wave liquid sensing system and its application for measurement of Japanese tea

In this paper, we report on the development of a practical compact and stable sensing system with a shear horizontal surface acoustic wave (SH-SAW) sensor for liquid. First, the oscillation circuits for the liquid-phase sensor based on the SH-SAW device is discussed. Two sensor outputs, i.e., frequency and amplitude, are required for evaluating the liquid properties. To monitor the amplitude, an automatic gain control amplifier (AGC amp) is utilized in the oscillation circuit. The developed sensing system has a low standard deviation of noise that is less than the temperature coefficient of the frequency of the dual SH-SAW sensor and from which the detection limit is estimated. The dynamic range of the developed SH-SAW sensing system is also estimated. The system is applied for the measurement of Japanese tea. The results indicate that the slight differences among teas can be detected by the SH-SAW liquid sensing system.

Automatic gain-controlled bidirectional add-drop amplifier for dynamically reconfigurable bidirectional WDM networks

An automatic gain-controlled bidirectional add-drop amplifier (BADA) has been realized by incorporating pump-controlled bidirectional and unidirectional EDFAs. By using the BADAs, we demonstrate a dynamically reconfigurable bidirectional wavelength division multiplexed (WDM) ring network. The BADA enables dynamic add-drops of wavelength-interleaved bidirectional signals and protects surviving signals against the impairments induced by dynamic network reconfigurations.

A Floating-Point ADC with Variable Gain Pipeline Stages

Typically an automatic gain control (AGC) amplifier is needed in a receiver to control the amplitude of the signal at the input of the ADC. To get rid of the AGC, a floating-point pipelined analog-to-digital converter (FP-ADC), which consists of variable gain stages, is presented. The frontend pipeline stages of the ADC use a larger gain if the value of the signal is small. If the value of the signal is large, they act as typical pipeline stages. Thus, the small values of the signal are converted using higher resolution than larger values. The dynamic range of the ADC is increased and a separate AGC is not needed.

43 Gbit∕s automatic gain control amplifier based on InP SHBT technology

A high bandwidth automatic-gain-control (AGC) amplifier has been designed and characterised. Fabricated in InP single-heterojunction-bipolar transistor (SHBT) technology, the measured bandwidth of the amplifier is 36 GHz with maximum small signal gain 22 dB. Capable of operating at 43 Gbit/s, this is believed to be the fastest AGC amplifier reported to date.

A transmit/receive IF chip set for WCDMA mobiles in 0.35 μm CMOS

An implementation of the IF section of WCDMA mobile transceivers with a set of two chips fabricated in an inexpensive 0.35-/spl mu/m two-poly three-metal CMOS process is presented. The transmit/receive chip set integrates quadrature modulators and demodulators, wide dynamic range automatic gain control (AGC) amplifiers, with linear-in-decibel gain control, and associated circuitry. This paper describes the problems encountered and the solutions envisaged to meet stringent specifications, with process and temperature variations, thus overcoming the limitations of CMOS devices, while operating at frequencies in the range of 100 MHz-1 GHz. Detailed measurement results corroborating successful application of the new techniques are reported. A receive AGC dynamic range of 73 dB with linearity error of less than /spl plusmn/2 dB and spread of less than 5 dB for a temperature range of -30/spl deg/C to +85/spl deg/C in the gain control characteristic has been measured. The modulator measurement shows a carrier suppression of 35 dB and sideband/third harmonic suppression of over 46 dB. The core die area of each chip is 1.5 mm/sup 2/.