Automatic Amplitude Control Loop Research Articles

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm2. By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

DESIGN AND ANALYSIS OF A 2.4 GHz HYBRID TYPE AUTOMATIC AMPLITUDE CONTROL VCO WITH FORWARD NOISE REDUCTION

This paper presents a voltage-controlled oscillator (VCO) with automatic amplitude control (AAC) loop. The proposed AAC VCO employs a hybrid type AAC loop and targets the Industrial, Scientific and Medical (ISM) band applications. The proposed AAC loop can also prevent the AAC from generating extra noise to the VCO and avoid stability problem which is common for conventional AAC loop. Detail transient analysis of this AAC VCO is derived. Based on this analysis, design steps applicable for such type of AAC loop is obtained. Measurement result shows the peak amplitude variation over the operation range of 2.25–2.54 GHz is less than 9 mV (without the AAC loop, amplitude variation can be as large as 40 mV, or 22.2% for 180 mV amplitude). Power consumption of the proposed AAC VCO is 4.5 mW while the power consumed by the loop is 0.8 mW and phase noise is -105 dBc/Hz at 100 kHz offset frequency. Worst case settling time is less than 10.5 μs.

A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-$\mu \rm g$ Bias Stability and 20-$ \mu\rm g/\sqrt{{\hbox{Hz}}}$ Resolution

A fully differential CMOS readout circuit for SOI resonant accelerometer is reported. The readout circuit is essentially an oscillator, consisting of an oscillator and a low noise automatic amplitude control (AAC) loop. A differential sense resonator is proposed to facilitate fully differential circuit topology and improves the SNR under a 3.3-V supply. A second-order AAC loop filter and a novel chopper stabilized rectifier are employed in the AAC loop to remove the noises, in particular, the 1/f noise, and to minimize the phase noise caused by the amplitude stiffening effect. The strong driving feedthrough is avoided by separating the drive and sense operation in the time domain, while using the same electrodes. The complete resonant accelerometer operates under a 3.3-V supply and achieves 140-Hz/g scaling factor, 20 mug/radicHz resolution and 4 mug bias stability. The readout circuit draws 7 mA under 3.3-V supply.

Notice of Violation of IEEE Publication Principles: A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit

A multi-rate 9.953-12.5-GHz low phase noise LC oscillator was realized in a 90-GHz f/sub T/ 0.2 μm SiGe BiCMOS process. It achieves a 36% tuning range by combining a 35% open-loop frequency calibration range having a sub-0.1% residual error with a 1% closed-loop varactor frequency tuning. The oscillator gain is below 130 MHz/V, while having less than 10% variation over the entire tuning range. The varactor is realized with multiple parallel-connected cells consisting of constant capacitors and voltage-controlled resistors that bring a lower process variation and a higher quality factor in comparison with standard diode and MOS varactors. A dual regulator architecture was used to provide both high PSRR and low output voltage noise. The supply pushing was reduced below 100 kHz/V by using a pushing cancellation circuit that balances the negative and positive voltage coefficients of the different nonlinear capacitors connected to the LC tank. A discrete-time automatic amplitude control loop using a variable tail resistor architecture was implemented to optimize the VCO's phase noise performance. The VCO specifications include 9.953-12.5-GHz frequency range, 0.1% frequency calibration error, -122 dBc/Hz phase noise at 1 MHz offset, <3 kHz 1/f/sup 3/ corner frequency, <-80 dBc spurious tones, 250×400 μm/sup 2/ die area and 5-mA bias current from a 3.3-V supply.

Impact of AAC design on phase noise performance of VCOs

The automatic amplitude control (AAC) system is a servo-circuit of voltage-controlled oscillators (VCOs) that proves important for the practical implementation of fully integrated RF front-ends. Nevertheless, the noise contributed by the AAC can degrade the phase noise performance of the oscillator. In this paper, the time-varying noise transfer of the peak detector is analyzed, since it is recognized as the critical noise source in the simple AAC loop taken as reference. A fast rule to predict the noise spectral density at the peak detector output is given that substantially facilitates the estimate of the phase noise degradation on the VCO output. The analysis has been carried out both theoretically and by simulation; experimental validation has also been provided by means of a discrete-components test board. Guidelines for low-noise design of the peak detector of AAC are finally proposed.

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 /spl mu/A are drawn by the AAC circuit.