Relative to the Si industry, it is well known that the yield and cost of high performance III-V semiconductor devices and circuits have long been limited by low wafer volumes, increased substrate handling, the widespread use of metal liftoff techniques, and the use of time consuming electron beam lithography for sub ½ µm gate lithography. The silicon industry, on the other hand, has the benefit of high wafer volumes, highly automated cassette to cassette foundries, subtractive processing techniques, advanced deep sub micron optical lithography, and the Moore’s law paradigm (driving both equipment development and technology node development). Additionally, at a given technology node, the diameter of Si wafers processed in Si foundries has grown to 200-300mm. This in turn reduces cost of yielded product even further.As a result, the Si foundry environment has long been an attractive potential path for III-V device processing. What has been problematic, however, is that the low product volume of traditional III-V applications (such as RF and mixed signal), limited 100-150mm substrate diameter, and contamination concerns (due to use of Au and As based III-V compounds) have combined to limit the adoption of III-V materials by Si foundries. Thankfully, the recent substantial investment in gallium nitride (GaN) device technology may change this dynamic.GaN is chemically stable over most of the temperature range used in CMOS processing and is not perceived as inherently detrimental to CMOS from a contamination control perspective. This potential process compatibility with CMOS, and recent demonstrations of 200mm GaN on Si epitaxy, may enable GaN device technology to be gracefully phased in to aging 200mm CMOS foundries (to offset the decline of 200mm CMOS nodes). As a result, these foundries could potentially remain commercially viable and even thrive as 200mm GaN on Si power switching and RF applications in commercial and defense grow.To explore this possibility Raytheon has established a 200mm GaN on Si HEMT process within a commercial CMOS Si Foundry environment utilizing high yield Si-like processing techniques and Cu back end of line (BEOL) processes at Novati in Austin Tx. Our approach combines Raytheon’s 14 years of industry leading GaN HEMT experience (materials through system insertion) for defense applications with IQE’s own substantial materials know how, and Novati’s 200 & 300 mm Si foundry capability and expertise. To that end, based on our previous work1,2,3,4, we have implemented a Au-free, subtractively processed device cross section. The first mask release supporting this process cross section was released at Novati, our partner Si foundry, in 2013. More specifically, the mask set supports a 0.25µm GaN MISHEMT Front-End-Of-Line (FEOL) core transistor process that is reminiscent of cross sections used by traditional III-V foundries. The three metal coplanar waveguide (CPW) Back-End-Of-Line (BEOL) of the process, on the other hand, leverages single and dual damascene Cu interconnect technology developed for Si CMOS. Our Cu BEOL interconnects, however, have been adapted to handle the high current densities of GaN HEMTs and are in the process of being integrated with MIM capacitors and resistors to realize high performance RF circuits on the mask set.With our collaborator IQE, we have already demonstrated the scaling of GaN epitaxy to 200 mm via MBE (Raytheon) and MOCVD (IQE). Additionally, as shown in figure 1, process development using the mask set is well underway, and in fact transistor functionality has been demonstrated on 200mm wafers processed entirely at Novati's Si Foundry.As development continues, GaN HEMT material growth and process development will be optimized so that the performance of the all-Si foundry fabricated devices and circuits will be comparable to those fabricated in traditional III-V foundries on Si.
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Nov 14, 2019
Xiaoyuan Xie + 2
Open Access