Audio Delta-sigma Research Articles

A 111dB-SNDR 20kHz-BW Delta-Sigma Modulator with Auto-Zeroing and Class-AB Amplifier

This paper describes the design of a high-precision audio Delta-Sigma modulator. To guarantee the modulator linearity and resolution with a limited oversampling rate (OSR), 4th-order 1-bit architecture is chosen. Auto-zeroing technique is used to reduce offset and low-frequency noise. To optimize power consumption, the switched-capacitor loop filter is implemented by feedforward structure with a passive adder and class-AB two-stage amplifiers. A clock generator with optimized non-overlapping pulse widths is designed to improve precision. Simulation results in 180nm CMOS show that with a 10.24MHz sampling rate, the presented modulator achieves 111dB signal-to-noise-and-distortion ratio (SNDR) at 20kHz bandwidth (BW) and consumes 17.9mW power under 3.3V supply, corresponding to an excellent figure-of-merit (FoM) of 171.5dB. Simulation results in process corners and temperatures show that the modulator is robust over variations.

A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

Modeling, Measurement, and Analysis of Audio Frequency Ground Integrity for a TDMA Smartphone System

In this paper, we first propose a modeling method of arbitrary-shaped multilayer printed circuit board (PCB) ground planes and chassis of smartphones in the audio frequency range (20 Hz–20 kHz). The model is proposed to quickly and accurately analyze audio frequency ground voltage noise at an audio circuit that is induced from a time-division multiple access (TDMA) RF power amplifier (PA) while it is switching at an audio frequency during a call. Conventional 3-D electromagnetic (EM) simulation consumes enormous computation time and resources. However, the proposed method models the ground network as a resistive ground distribution network based on the finite-difference method and saves the computation time and resources. We verified the proposed modeling method by comparing ground noise coupling levels obtained from the proposed model, 3-D EM simulation, and measurement in the time and audio frequency domains. The proposed model showed 3.4% and 22.8% differences in the time domain and 3.8% and 14.8% differences at the 217-Hz fundamental frequency in the frequency domain, respectively, compared to 3-D EM simulation and measurement. Furthermore, we used the proposed model to analyze the ground noise coupling between audio circuits and TDMA RF PAs integrated on various designs of PCBs. To verify the correlation between the analysis and the actual performance degradation of audio circuits, we fabricated the PCBs, mounted commercial audio Delta–Sigma modulators and RF PAs, and measured the output of the modulators. The correlation is verified from the modulator on the PCB with the least ground noise coupling showing a spurious-free dynamic range 40.5 dB higher than the modulator on the PCB with the largest ground noise coupling.

A 300-<inline-formula> <tex-math notation="LaTeX">$\mu\text{W}$</tex-math> </inline-formula> Audio <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math> </inline-formula> Modulator With 100.5-dB DR Using Dynamic Bias Inverter

This paper presents a micropower audio delta-sigma (ΔΣ) modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation caused by the cascode transistors in the inverter is resolved by using active parasitic compensation. This maximizes both gm/ID ratio and slew rate of the inverter-based integrator, while compensating process, voltage, and temperature (PVT) variations. To verify the effectiveness of the proposed technique, a single-bit third-order ΔΣ modulator is implemented in a 0.18 μm CMOS technology. The prototype modulator achieves 97.7 dB SNDR, 98.6 dB SNR, and 100.5 dB DR in a 20-kHz signal bandwidth, while consuming only 300-μW from a 1.8 V supply. This corresponds to a state-of-the-art Schreier's FoM of 178.7 dB. The results are fully verified under variable supplies and temperatures.

Dual-channel multiplexing technology and its realization in interpolation filter in stereo audio sigma-delta DAC

In this paper, we propose a novel low-cost and hardware-efficient digital interpolation filter applied to stereo audio sigma-delta digital-to-analog converter. The paper presents a dual-channel multiplexing structure and utilizes memories to realize the first stage half-band filter in the interpolation filter for reaching the goal of saving chip area. The reorder technique is derived to synchronize the two channels after multiplexing. The design is implemented on 0.18 µm 1.8/3.3 V 1P5M CMOS process. The measurement results show that the signal-to-noise ratio of the DAC achieves 106 dB and the digital part of chip only takes a proportion of 0.198 mm2 with only 0.65 mW power consumption. The proposed design decreases the area and power dissipation, meanwhile, gives much more design margin to the analog part of Σ-Δ DAC, which benefits for the mixed-signal system design.

A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators

A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators

Jitter-free return-to-zero generator

A return-to-zero generator based on a delay-locked loop is used to create a pulse free of system clock jitter, power supply disturbance and substrate noise peaks inherent to mixed-signal devices. An audio continuous-time delta-sigma converter equipped with this generator is able to overcome the jitter barrier and achieve far better performances.

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver

A 0.8 V third-order multibit DeltaSigma DAC with headphone driver is described. It is the first sub-1 V audio DeltaSigma DAC with integrated on-chip headphone driver. The dual-channel operation in digital section was efficiently realized with a time-interleaved single-channel hardware and extra registers. Using novel DAC architecture suitable for low-voltage operation, the analog section requires only one opamp per channel for the D/A conversion, low-pass filtering, and driving the headphone. Two prototype ICs (separate digital and analog chips), implemented in a 0.35 mum CMOS process, achieved an 88 dB dynamic range, while consuming 2.6 mW from a 0.8 V supply.

Research on Characteristics of Audio DAC Sigma-Delta Modulator on Field Programmable Gate Array

The original architectural scheme of a designed audio Sigma Delta DAC on the FPGA whose application in a computer sound system allows refusing of an analogue sound track and improving the sound quality is presented. Modelling results of the audio interpolator filters transmission characteristics and the Sigma Delta modulator’s quantization noise parameters are given. It was determined that requirements are met best by a CIC filter amplitude frequency characteristics when the interpolation multiplier is L=8, the number of stages is N = 6, the input string length is 16 bits, the output string length is 31 bits, and the discretization frequency is 2.8224 MHz. The results of the modulator modelling showed that when a sound signal frequency band is of 20 kHz the modulator’s effective number of bits is 16, while the quantization noise power is minus 118dB. The modelling results are also proven by the experimental research when a DAC has been realized with Xilinx Spartan XC3S400-4PQ208 on the array. Ill. 12, bibl. 4 (in English; summaries in English, Russian and Lithuanian).

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.

A 113-dB DSD audio ADC using a density-modulated dithering scheme

A stereo audio delta-sigma A/D converter is implemented to support both the standard pulse-code modulation audio and the direct stream digital (DSD) output format. It provides all the standard audio rates up to 192 kHz. A sixth-order, single-bit modulator is employed to achieve the noise performance as well as the bitstream output required by the DSD format. A novel density-modulated dithering scheme is utilized to dramatically reduce the tone level in the signal band without compromising the stability of the high-order modulator. This analog-to-digital converter achieves a dynamic range of 113 dB and a total harmonic distortion +N of 105 dB. It is fabricated in a 0.35-/spl mu/m CMOS process with a die size of 10.5 mm/sup 2/.

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-/spl mu/m, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits.

A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range

A 5-V 24-b audio delta-sigma A/D converter has been developed. The single chip integrates stereo delta-sigma modulators, a voltage reference, and a decimation filter. A fourth-order cascaded delta-sigma modulator using a local feedback technique was employed to avoid overload without sacrifice in noise performance. A two-stage decimation filter architecture which reduces digital noise was developed. A new multistage comb filter was used for the first-stage, and a bit-serial finite impulse response (FIR) filter was used for the second stage. The 25.8 mm/sup 2/ chip was fabricated in 0.7-/spl mu/m CMOS with low threshold MOS devices. Measured results show 111 dB dynamic range and 103 dB peak signal-to-(noise plus distortion)S/(N+D).