Asynchronous Transfer Mode Switching Network Research Articles

Rate-based congestion control in ATM switching networks using a recursive digital filter

The present paper proposes a control-theoretic approach to design rate-based controllers in order to flow-regulate the best-effort service in asynchronous transfer mode (ATM) switching networks. The proposed control uses a recursive digital filtering controller, where the control parameters can be designed to ensure the stability of the control loop in a control-theoretic sense. The stability of closed-loop congestion-controlled systems is analyzed by using Schur–Cohn stability criterion, which leads to certain necessary and sufficient stability condition under which the controlled ATM switching network is asymptotically stable in terms of buffer occupancy. Such proposed stability condition is then shown to be a key tool in designing a wide scope of adaptive controllers. Further, we demonstrate that a fair share of the available bandwidth at the bottleneck node can be achieved according to the proposed control policy. Simulations are performed that show good performance of both local area networks and wide area networks if implemented by the proposed control schemes.

Designing ATM Switching Networks

Designing ATM Switching Networks

New fiber-optic ATM switching networks using optical code-division multiple access for broadband communication applications

We design new fiber-optic asynchronous-transfer-mode (ATM) networks which are based on incoherent optical code-division multiple access (CDMA). To eliminate the throughput bottleneck, optical signal processing is used in the proposed switching network to guarantee a high processing speed which is required by incoherent optical CDMA. This in turn can support real-time broadband communication services. Because strict optical orthogonal codes (OOCs) are employed, both cross-correlation and autocorrelation constraints are strictly limited to be "1" for variable-bitrate (VBR) and constant-bit-rate (CBR) data communications. In the VBR case, the use of strict OOCs can guarantee a lower bit error rate than using conventional OOCs. Moreover, the proposed ATM switching network can efficiently support CBR and VBR communications (e.g. HDTV and video conferencing with the MPEG-2 standard), with no increase of system bandwidth and no change of optical CDMA encoder/decoder. Simple theory and code construction of strict OOCs are presented. Moreover, error correction codes are used in fiber-optic CDMA networks to improve the system performance.

Optical beam direction compensating system for board-to-board free space optical interconnection in high-capacity ATM switch

In interconnections between bookshelf-assembled asynchronous transfer mode (ATM) switch boards, a large number of micro-optical signal beams can be optically interconnected by a beam direction compensating system using a vertical cavity surface emitting laser, an x-y beam positioning sensor and a beam deflector made of an adjustable liquid prism. This beam direction compensating system can suppress the decrease in coupling efficiency between transmitters and receivers to no more than 15%, even if boards are inserted and extracted repeatedly, and are shocked repeatedly at a high intensity of 100 G. The compensation is very fast (20 ms). Furthermore, various optical interconnections necessary for ATM switching networks can be achieved by beam deflectors of a liquid crystal microprism array. In this preliminary study, we fabricate no more than eight-channel optical interconnections. However, since one surface emitting laser diode can have many channels in a small area (64 channels per 4 mm/sup 2/) and the aperture of this adjustable liquid prism is wide (28 mm in diameter) and uniform, a huge number of optical interconnection channels is possible using this system.

A study of performance issues of the ATLAS event selection system based on an ATM switching network

The next generation of High Energy Physics experiments, ATLAS and CMS, proposed at the CERN Large Hadron Collider (LHC), will place heavy demands on the data acquisition and on-line filtering systems. Asynchronous Transfer Mode (ATM) is a candidate technology to implement the high performance network in the data collection system for the ATLAS experiment. This work presents the results of modeling and simulation studies which aim at integrating the detailed organization of the detector read-out, the trigger requirements and the capabilities of ATM switching networks. The status of hardware development of small scale demonstrators is outlined.

Nonblocking atm switching networks for variable bit rate traffic

AbstractAn asynchronous transfer mode (ATM) switching network handles not only traffic of various bandwidths, but multirate bursty traffic including constant bit rate and variable bit rate traffic as well. Consequently, to simplify the design and operation of the facility, it is desirable for the ATM network to be nonblocking at the connection level. The nonblocking issue when the network must handle variable bit rate traffic is related closely to the connection admission control (CAC) employed.While the nonblocking feature for a linear CAC function has been studied in the past, the relation between the switching network cell‐level quality and non‐blocking characteristic for a specific CAC premising variable bit rate traffic has not been analyzed.This paper examines a nonlinear CAC, evaluates the cell loss probability and statistical multiplex gain when it is applied and proposes the definition for a non‐blocking feature called “(p0, p, q) nonblocking.” Next, a cell distribution‐type, three‐stage ATM switching network is shown that ensures (p0, p, q) nonblocking for traffic including multicast connections without expanding the internal link capacity either in terms of space or speed.

ATM switching network with route-associated buffers and its traffic-handling characteristics

Asynchronous transfer mode (ATM) switching is studied widely as the switching method in the broadband ISDN and numerous switching methods have been proposed. In most of those methods, the deterioration of the throughput due to the internal collision of the cells is prevented in the switching network by a complex control protocol or by increasing the internal speed. In the highspeed broadband switching system such as ATM, however, it is desirable for the system that the structure and the control be simple, the internal speed not be increased, and the highly efficient switching network be realized with a nonblocking property. This paper attempts to satisfy the forementioned requirements and proposes the route-associated buffer system in which the buffers are provided corresponding to the input and the output route, while improving the efficiency of the use of the buffers. The network configuration and the traffic control process are presented. In the traffic analysis, the poling model is defined, where the number of cells to be taken out from the individual buffer is adjusted according to the number of waiting cells. The traffic processing performance of the switching network is analyzed using the approximate method of analysis for the cyclic multiple queues. The usefulness of the method is shown by numerical analysis and simulation.

Implementation of a 16 to 16 switching element for ATM exchanges

The authors describe the implementation of an asynchronous transfer mode (ATM) switching element with 16 inlets and 16 outlets at 600 Mb/s each. The single board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element was carried out by using advanced BiCMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queueing memory is treated in detail. A comparison between memory pooling or individual output queues is presented. By making the choice of the latter solution, the development schedule could be kept very tight. Second, the testability of the chips remains good despite the high gate complexity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Large-scale ATM multistage switching network with shared buffer memory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>