Asynchronous Transfer Mode Switch Fabric Research Articles

ATM over ADSL probe in Telecom Italia environment

This paper covers access network performance analysis by deploying asynchronous transfer mode (ATM) over ADSL within the Telecom Italia experimental department “EXANET” (experimental ATM network). In this scenario, data traffic leaves customer site as ATM traffic running over ADSL modem links, it is aggregated via digital subscriber line access multiplexer (DSLAM) at the central office (CO) and then dropped onto the high-speed ATM switching fabric. The Italian telephone company was eager to use ADSL as a way to relieve congestion on their circuit-switched voice telephony system, increasingly bogged down by the growth of the Internet and by long data transmissions.

Modeling and formal verification of the Fairisle ATM switch fabric using MDGs

In this paper, we present several techniques for modeling and formal verification of the Fairisle asynchronous transfer mode (ATM) switch fabric using multiway decision graphs (MDGs). MDGs represent a new class of decision graphs which subsumes Bryant's reduced ordered binary decision diagrams (ROBDDs) while accommodating abstract sorts and uninterpreted function symbols. The ATM device we investigated is in use for real applications in the Cambridge University Fairisle network. We modeled and verified the switch fabric at three levels of abstraction: behavior, and register transfer level (RTL) and gate levels. In a first stage, we validated the high-level specification by checking specific safety properties that reflect the behavior of the fabric in its real operating environment. Using the intermediate abstract RTL model, we hierarchically completed the verification of the original gate-level implementation of the switch fabric against the behavioral specification. Since MDGs avoid model explosion induced by data values, this work demonstrates the effectiveness of MDG based verification as an extension of ROBDD-based approaches. All the verifications were carried out automatically in a reasonable amount of CPU time.

Three‐stage high‐performance optoelectronic asynchronous transfer mode switch: design and performance

We explore the possibility of enhancing very large scale integration (VLSI) electronic switch structures using reconfigurable freespace optical chip-to-chip interconnects. We present a novel technological approach to the realization of an output queued asynchronous transfer mode (ATM) switching fabric within a low-blocking, three-stage network configuration by employing both electronic and optical switching stages with reduced cross-office transfer rates. The first and third stages are implemented by the selective reading/writing from/to a sectorized optically accessible random access memory (known as opto-RAM) currently under development in our laboratory. The second (central) stage uses holographic fan-out/selective fan-in optics to implement a freespace photonic crossbar switch. We assess the performance of the ATM switch fabric using computer simulation as well as analytic techniques.

Multigigabit multichannel optical interconnection module for broadband switching system

This paper describes optical transmitter and receiver modules for package-to-package interconnection in broadband switching networks such as an asynchronous transfer mode switch fabric. These modules, which include the multiplexer and demultiplexer, can reduce the number of connections and the problem of skew between links. Five-channel optical transmitter and receiver modules were fabricated and demonstrated at 2.8 Gbit/s with a power dissipation of 4.5 W per channel. Moreover, temperature-insensitive optical interconnection was successfully demonstrated by driving a laser with a constant bias current over the threshold and by deducting the optical signal offset. The output power of the transmitter module was -4.2 dBm. Nonuniformity of the transmitter output powers across the range of optical channels was <2.1 dB. Receiver sensitivity for a bit error rate of 10/sup -11/ was -9.3 dBm. Nonuniformity of the receiver sensitivities was <1.5 dB. The power penalty of the receiver sensitivity due to crosstalk was 1 dB. The connection distance was >250 m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An asynchronous data-driven event-building scheme based on ATM switching fabrics

Asynchronous transfer mode (ATM) packet-switching network technology is proposed as the interconnect for building high-performance, scalable data acquisition architectures. This paper introduces the relevant characteristics of ATM and describes components for the construction of an ATM-based event builder: (1) a multi-path, self-routing, scalable ATM switching fabric, (2) an experimental high performance workstation ATM-interface, and (3) a VMEbus ATM-interface. The requirement for traffic shaping in ATM-based event-builders is discussed and an analysis of the performance of several such schemes is presented. >

Technologies for Broadband Switching

For an asynchronous transfer mode (ATM) network to provide a wide range of services, high-capacity and low-cost network elements are needed. The capacity and cost of these elements are determined by the costs of the underlying hardware and software devices necessary to build them: ATM line cards, switching fabrics, and control structures. These devices, in turn, are built upon the advanced technologies of digital devices, optics, algorithms, and architectures. In this paper, we explore the applications of these technologies to develop ATM line cards, ATM switching fabrics, and ATM control structures.

A reconfigurable ATM switch fabric for fault tolerance and traffic balancing

A large-scale asynchronous transfer mode (ATM) switch fabric that can be constructed with currently feasible technology is proposed. Based on analysis of the technology, it is found that module interconnection becomes the bottleneck for a large fast packet switch. Fault tolerance for the switch is achieved by dynamic reconfiguration of the module interconnection network. The design improves system reliability with relatively low hardware overhead. An abstract model of the replacement problem for the design is presented, and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found, and a fast replacement algorithm is given. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. The authors formulate this traffic flow assignment problem for the switch fabric and show that the problem is NP-hard. A simple heuristic algorithm is proposed, and an example is given. >