Asynchronous Transfer Mode Ring Research Articles

Formal Verification of Simulation Traces Using Computation Slicing

Concurrent and distributed systems, such as system-on-chips (SoCs), present an immense challenge for verification due to their complexity and inherent concurrency. Traditional approaches for eliminating errors in concurrent and distributed systems include formal methods and simulation. We present an approach toward combining formal methods and simulation in a technique called predicate detection (aka runtime verification), while avoiding the complexity of formal methods and the pitfalls of ad hoc simulation. Our technique enables efficient formal verification on execution traces of actual scalable systems. Traditional simulation methodologies are woefully inadequate in the presence of concurrency and subtle synchronization. The bug in the system may appear only when the ordering of concurrent events is different from the ordering in the simulation trace. We use a partial order trace model rather than the traditional total order trace model and we get the benefit of properly dealing with concurrent events and especially of detecting errors from analyzing successful total order traces. Surprisingly, checking properties, even on a finite partial order trace, is NP-complete in the size of the trace description (aka state-explosion problem). Our approach to ameliorating state explosion in partial order trace model uses two techniques: 1) slicing and 2) exploiting the structure of the property itself-by imposing restrictions-to evaluate its value efficiently for a given execution trace. Intuitively, the slice of a trace with respect to a property is a subtrace that contains all of the global states of the trace that satisfy the property such that it is computed efficiently (without traversing the state space) and represented concisely (without explicit representation of individual states). We present temporal slicing algorithms with respect to properties in temporal logic RCTL+. We show how to use the slicing algorithms for efficient predicate detection of design properties. We have developed a prototype system, partial order trace analyzer (POTA), which implements our algorithms. We verify several scalable and industrial protocols, including CORBA's general inter-ORB protocol, PCI-based system-on-chip, ISO's asynchronous transfer mode ring, cache coherence, and mutual exclusion. Our experimental results indicate that slicing can lead to exponential reduction over existing techniques, such as the ones in SPIN model checker, both in time and space

Comparison of SPIN and VIS for protocol verification

In this paper, we compare and contrast SPIN and VIS, two widely used formal verification tools. In particular, we devote special attention to the efficiency of these tools for the verification of communications protocols that can be implemented either in software or hardware. As a basis of our comparison, we formally describe and verify the Asynchronous Transfer Mode Ring (ATMR) medium access protocol using SPIN and its hardware model using VIS. We believe that this study is of particular interest as more and more protocols, like ATM protocols, are implemented in hardware to match high-speed requirements.

Waiting time estimates in symmetric ATM-oriented rings with the destination release of used slots

This paper considers the basic access mechanism in asynchronous transfer mode (ATM)-oriented rings which, like Orwell, ATM ring, and ALine, apply destination release of used slots. The released slots may be reused by the destination station, or in some protocols, they must be given to the next station. Such a mechanism can be modeled by a multiple-server multiqueue system, where switchover times between consecutive polling instants of the queues are nonzero. The server polls the queues according to a certain polling discipline, which is dependent on the service time. This paper presents approximate mean minipacket waiting times in such systems. The approximation is based on a polling queueing model with Markovian server routing. Poisson arrivals and a symmetric workload model for minipackets having a full and partial traffic matrix are assumed. The performance characteristics are compared between the alternative options.

An ATM cell format and media access protocol for a network of switch-interconnected shared-medium ATM rings

The asynchronous transfer mode ring (ATMR) protocol suffers from addressing and latency-related limitations when applied to large networks. This paper proposes a cell format and media access protocol (MAP) applicable to a switch-interconnected ATMR (SI-ATMR) network. The SI-ATMR network has a small ring latency, has no addressing limitations, and provides fair access and guaranteed quality of service (QoS).

A performance comparison of cell-based local area networks

Recently, the deployment of Asynchronous Transfer Mode (ATM) technology in the Local area (ATM LANs) has received much attention. Such interest is motivated by the simplifications offered in supporting ATM in the local area, which may result in rapid deployment of ATM-based Broadband Integrated Services Digital Networks (B-ISDN). Cell-based LANs, viz. ATM LANs, provide efficient bandwidth utilization ::.md en-or recovery, as well as simplified priority implementation. We compare the performance of three cell-based LAN alternatives: the Distributed Queue Dual bus (DQDB) (1), Asynchronous Transfer Mode Ring (ATMR) (2) and switch-based ATM LANs employing ATM switches (3). We develop a versatile simulation model which is used to study the merits of each alternative.

Traffic control in asynchronous transfer mode

The definition of traffic descriptors is discussed, and cell delay variation (CDV) that complicates usage parameter control (UPC) is analyzed. A generic flow control protocol that facilitates UPC is described. It is based on the asynchronous transfer mode ring (ATMR) protocol. The ATMR-GFC protocol achieves the guarantee of bandwidth by a cyclic reset scheme. Bandwidth calculation methods for connection admission control are reviewed from the viewpoint of different time scales. Both a real-time and offline calculation method are discussed. A combined method taking advantage of both methods is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>