Asynchronous Transfer Mode LAN Research Articles

A control-theoretic approach to the design of an explicit rate controller for ABR service

We present a control-theoretic approach to the design of closed-loop rate-based flow control in high-speed networks. The proposed control uses a dual proportional-plus-derivative controller, where the control parameters can be designed to ensure the stability of the traffic patterns and propagation delays. We show how the control mechanism can be used to design a controller to support ABR service based on feedback of explicit rates (ERs). We demonstrate the excellent transient and steady-state performance of the controller through a number of examples. We also show experimental results that have been obtained from our asynchronous transfer mode (ATM) testbed, which consists of two interconnected ATM LANs, one located in Princeton, NJ, and the other in Berlin, Germany, with an all-software ER-controller implementation.

Performance of TCP over UBR in ATM with EPD and virtual queuing techniques

While both available bit rate (ABR) and unspecified bit rate (UBR) services can be used to support data traffic in asynchronous transfer mode (ATM), many ATM switch vendors consider UBR to be more attractive because of its low implementation cost in comparison with ABR. However, since there is no congestion control at the cell level in UBR and cells are simply discarded when buffer overflow occurs, the effective throughput of transmission control protocol (TCP) can degrade significantly over UBR service in a congested network. Early Packet Discard (EPD) techniques have been proposed by Romanow and Floyd (Dynamics of TCP traffic over ATM networks, IEEE Journal on Selected Areas in Communications 13 (4) (1995) 633–641) and shown to improve the throughput of TCP over ATM. In our earlier work (A simulation study of TCP performance in ATM networks with ABR and UBR services, in: Proceedings of the International Phoenix Conference on Computers and Communications, March 1996), we have shown that TCP with EPD can suffer significant degradation in fairness of throughputs among competing VCs in a congested ATM LAN environment, but the degree of fairness can be improved by using per-VC accounting/queuing techniques. In this paper, we continue our studies in designing better and low cost methods for the support of TCP over ATM. We apply the virtual queuing technique proposed in Chiussi et al. (Virtual queuing techniques for ABR service: improving ABR/VBR interaction, Infocom'97) to emulate on a FIFO queue the service provided by per-VC queuing. This technique requires low implementation cost and delivers performance of TCP over UBR comparable to the expensive per-VC queuing technique. Simulation results are presented to demonstrate that our technique combined with EPD can drastically improve the performance of TCP over UBR service.

A performance comparison of cell-based local area networks

Recently, the deployment of Asynchronous Transfer Mode (ATM) technology in the Local area (ATM LANs) has received much attention. Such interest is motivated by the simplifications offered in supporting ATM in the local area, which may result in rapid deployment of ATM-based Broadband Integrated Services Digital Networks (B-ISDN). Cell-based LANs, viz. ATM LANs, provide efficient bandwidth utilization ::.md en-or recovery, as well as simplified priority implementation. We compare the performance of three cell-based LAN alternatives: the Distributed Queue Dual bus (DQDB) (1), Asynchronous Transfer Mode Ring (ATMR) (2) and switch-based ATM LANs employing ATM switches (3). We develop a versatile simulation model which is used to study the merits of each alternative.

The Tera project: a hybrid queueing ATM switch architecture for LAN

The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns. >

Finding the right ATM switch for the market

The asynchronous transfer mode (ATM) promises to be the ultimate on-premise internetworking technology. Its high-bandwidth uniform switches can transfer graphics, audio, video. and text from application to application at much higher speeds than now available. In fact, ATM may well be the technology that brings the computer and communications industries together. Because ATM as a public service offering by telecommunications companies will probably not be in place before 1996-1997, the authors focus on the ATM LAN and the corporate backbone. Most of the proposals on the internal architecture of the ATM switch are still at a research-and-evaluation stage, based on the switching architectures of the 1970s and 198Os. Various objectives, such as blocking, routing, performance and VLSI implementation, motivated past work. Although these attributes are essential, they don't address concerns important to the commercial ATM market, such as the general cost of ownership and incremental deployment, scalability, reliability, and efficient bandwidth utilization. The few ATM switches on the market today embody attributes that meet current demands but must evolve to meet the future. The authors assess the architectural characteristics deemed necessary for the ATM switch, providing an overview of its purpose and protocols, and summarize key ATM switch proposals. They summarize commercial market requirements and profile several commercially available systems to show the current gap between the research community and the commercial market, providing a model for the future. >