Asynchronous Sequential Logic Circuits Research Articles

A Novel Asynchronous CA Neuron Model: Design of Neuron-Like Nonlinear Responses Based on Novel Bifurcation Theory of Asynchronous Sequential Logic Circuit

This paper presents a novel asynchronous sequential logic circuit neuron model, the nonlinear dynamics of which is described by an asynchronous cellular automaton. As a novel theoretical analysis tool for the model, a continuous-discrete hybrid Poincare map is derived. The map reveals that the presented model can reproduce fundamental dynamic properties and typical bifurcation mechanisms of a biologically plausible neuron model. Using the bifurcation analysis results, systematic design methods of the presented model are proposed. It is shown that the design methods enable the presented model to reproduce typical nonlinear response curves of neurons as well as their underlying bifurcation mechanisms. In addition, the model is implemented in a field programmable gate array and experiments validate its operation. It is shown that the presented model can be implemented by fewer circuit elements and consumes lower power compared to typical conventional neuron models.

An Asynchronous Recurrent Network of Cellular Automaton-Based Neurons and Its Reproduction of Spiking Neural Network Activities

Modeling and implementation approaches for the reproduction of input-output relationships in biological nervous tissues contribute to the development of engineering and clinical applications. However, because of high nonlinearity, the traditional modeling and implementation approaches encounter difficulties in terms of generalization ability (i.e., performance when reproducing an unknown data set) and computational resources (i.e., computation time and circuit elements). To overcome these difficulties, asynchronous cellular automaton-based neuron (ACAN) models, which are described as special kinds of cellular automata that can be implemented as small asynchronous sequential logic circuits have been proposed. This paper presents a novel type of such ACAN and a theoretical analysis of its excitability. This paper also presents a novel network of such neurons, which can mimic input-output relationships of biological and nonlinear ordinary differential equation model neural networks. Numerical analyses confirm that the presented network has a higher generalization ability than other major modeling and implementation approaches. In addition, Field-Programmable Gate Array-implementations confirm that the presented network requires lower computational resources.

Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.

A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

A Generalized Rotate-and-Fire Digital Spiking Neuron Model and Its On-FPGA Learning

A generalized rotate-and-fire digital spiking neuron model that can be implemented by a simple asynchronous sequential logic circuit is proposed. The model can exhibit various nonlinear phenomena and responses to stimulation inputs. It is shown that the model can reproduce five types of inhibitory responses of Izhikevich's simplified ordinary differential equation neuron model. In addition, field programmable gate array experiments show that a learning algorithm enables the model to automatically reproduce nonlinear responses of a biological neuron and neuron models in the neuron simulator.

New Dimensions in Teaching Digital Electronics: A Multimode Laboratory Utilizing NI ELVIS IITM, LabVIEW and NI Multisim

Over the years, conventional Laboratories in African Universities have been hampered by inadequate resources in terms of the required hardware, space and skilled personnel to administer them. This paper describes a multi-dimensional approach to experimentation, developed by the Makerere University iLabs Project Team, hereafter referred to as iLABS@MAK. The two dimensional approach involves both Virtual Labs and Online Laboratories designed to address laboratory deficiencies in Digital Electronics, encompassing five courses in the curricula of the Bachelor of Science (B.Sc) in Computer, Electrical and Telecommunication Engineering Programs. A digital Online Laboratory, the Makerere University Digital iLab (MDEi) supporting experiments in the fields of combinational logic circuits and asynchronous sequential logic circuits has been developed. The laboratory utilizes the National Instruments Educational Laboratory Virtual Instrumentation Suite (NI ELVIS IIâ?¢) platform, the Laboratory Virtual Instrument Engineering Workbench (LabVIEW) graphical programming environment and NI Multisim. Typical experiment setups supported by the MDEi are presented

Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems

Asynchronous Sequential Machine Design and Analysis provides a lucid, in-depth treatment of asynchronous state machine design and analysis presented in two parts: Part I on the background fundamentals related to asynchronous sequential logic circuits generally, and Part II on self-timed systems, high-performance asynchronous programmable sequencers, and arbiters.Part I provides a detailed review of the background fundamentals for the design and analysis of asynchronous finite state machines (FSMs). Included are the basic models, use of fully documented state diagrams, and the design and characteristics of basic memory cells and Muller C-elements. Simple FSMs using C-elements illustrate the design process. The detection and elimination of timing defects in asynchronous FSMs are covered in detail. This is followed by the array algebraic approach to the design of single-transition-time machines and use of CAD software for that purpose, one-hot asynchronous FSMs, and pulse mode FSMs. Part I concludes with the analysis procedures for asynchronous state machines.Part II is concerned mainly with self-timed systems, programmable sequencers, and arbiters. It begins with a detailed treatment of externally asynchronous/internally clocked (or pausable) systems that are delay-insensitive and metastability-hardened. This is followed by defect-free cascadable asynchronous sequencers, and defect-free one-hot asynchronous programmable sequencers--their characteristics, design, and applications. Part II concludes with arbiter modules of various types, those with and without metastability protection, together with applications.Presented in the appendices are brief reviews covering mixed-logic gate symbology, Boolean algebra, and entered-variable K-map minimization. End-of-chapter problems and a glossary of terms, expressions, and abbreviations contribute to the reader's learning experience. Five productivity tools are made available specifically for use with this text and briefly discussed in the Preface.Table of Contents: I: Background Fundamentals for Design and Analysis of Asynchronous State Machines / Introduction and Background / Simple FSM Design and Initialization / Detection and Elimination of Timing Defects in Asynchronous FSMs / Design of Single Transition Time Machines / Design of One-Hot Asynchronous FSMs / Design of Pulse Mode FSMs / Analysis of Asynchronous FSMs / II: Self-Timed Systems/ Programmable Sequencers, and Arbiters / Externally Asynchronous/Internally Clocked Systems / Cascadable Asynchronous Programmable Sequencers (CAPS) and Time-Shared System Design / Asynchronous One-Hot Programmable Sequencer Systems / Arbiter Modules

Hazards, critical races, and metastability

The various modes of failure of asynchronous sequential logic circuits due to timing problems are considered. These are hazards, critical races and metastable states. It is shown that there is a mechanism common to all forms of hazards and to metastable states. A similar mechanism, with added complications, is shown to characterize critical races. Means for defeating various types of hazards and critical races through the use of one-sided delay constraints are introduced. A method is described for determining from a flow table situations in which metastable states may be entered. A circuit technique is presented for extending a previously known technique for defeating metastability problems in self-timed systems. It is shown that the use of simulation for verifying the correctness of a circuit with given bounds on the branch delays cannot be relied upon to expose all timing problems. An example is presented that refutes a plausible conjecture that replacing pure delays with inertial delays can never introduce, but only eliminate glitches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Application of bipartite graphs for achieving race-free state assignments

Achieving race-free state assignments is an important objective in the synthesis of asynchronous sequential logic circuits (ASLCs). Traditionally, adjacency diagrams are used to help identify and resolve race conditions; however, this approach has a high degree of computational complexity. This paper presents an efficient state assignment algorithm that utilizes a pattern matching technique to predict races and to eliminate the need for enumerative searches. More specifically, the race-free state assignment problem is formulated as the embedding of a bipartite connected graph onto an n-cube and achieves a near minimum number of state variables. This algorithm has been evaluated using several representative examples. Results show that the developed algorithm provides better performance than existing algorithms. Due to the simplicity of the bipartite representation of an n-cube, the developed algorithm is suitable for ASLC synthesis that may involve a relatively large number of states.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient modelling and synthesis procedure of asynchronous sequential logic elements

A model and procedure are developed for synthesising asynchronous sequential logic elements (ASLEs). This model represents the functional behaviour with a more compact form, and the procedure can synthesise them more efficiently than the traditional one. With the delineation of inputs as mode inputs,level inputs and edge inputs from the design specification, a set of equations can be generated which describes the logic module's functional behaviour. The calculated states from these equations have bipartite adjacency relationships, which can easily be mapped onto an n-cube to obtain race-free state assignments. This procedure can also be applied for the synthesis of an asynchronous sequential logic circuit (ASLC) which has many data inputs and a small number of control inputs.

Fault effects in asynchronous sequential logic circuits

The paper demonstrates the effects of single stuck-at faults in Huffman-model asynchronous sequential logic circuits (ASLCs). The fault effects include equivalent-state redundant faults, invalid-state redundant faults and state oscillations. Equivalent-state redundant faults in ASLCs may be generated by violation of the fundamental mode constraint noncritical races or delays. On the other hand, invalid-state redundant faults are caused either by the existence of invalid states, or by improperly assigning the ‘don&apos;t-care’ terms. State oscillations are generally caused by the presence of critical races. Based on the fault effects, this paper presents a set of rules for synthe-sising oscillation-free ASLCs in the presence of faults. As far as synthesising testable ASLCs is concerned, the race-free UDC state assignment is much better than STT state assignment.

Race-free state assignments for synthesizing large-scale asynchronous sequential logic circuits

A state assignment technique is introduced for synthesizing large-scale asynchronous sequential logic circuits (ASLCs). It provides a systematic and efficient approach for generating race-free state assignments. A race condition is classified as being either an intrinsic race (IR) or or a generated race. Intrinsic races decompose into two subclassifications: visible intrinsic races and hidden intrinsic races. Algorithms have been developed to identify and eliminate these races. A graph, referred to as a Node-Weight Diagram, facilitates the process of making state assignments and guarantees that no races are generated. Moreover, it provides a convenient and efficient method for investigating the implications of selecting from an allowed set of alternative race-free state assignments. The state assignment technique described adds cycles and states, as needed, to avoid IRs and always attempts to use the minimum or near-minimum number of state variables and states. This technique has been implemented and incorporated into an ASLC design automation system. Experimental results show that it provides significantly better results than other approaches in terms of the computation time required to make the assignments and the number of state variables required to achieve race-free ASLCs. >

Automating the design of asynchronous sequential logic circuits

The computer-aided design process described simplifies the task of designing asynchronous sequential logic circuits (ASLCs). It provides a highly structured, interactive approach for modeling sequential logic functions and for mapping these models into ASLC architectures and gate-level circuits. A design automation system that implements this process has been developed and tested. It contains five modules: (1) the behavioral descriptor, which maps the functional design specification into a primitive flow table; (2) the merger, which minimizes the number of states needed to implement the functional model; (3) the connector, which adds cycles and states, as needed, to avoid critical rates; (4) the assigner, which encodes the states and generates the state excitation table and output table; and (5) the equation generator, which eliminates static hazards and converts the state excitation table and output table into two-level, sum-of-product expressions for the state equations and output equations. This task-oriented system provides a convenient way to describe the functional behavior of sequential logic functions. It can reduce the design cycle time and improve the reliability of the overall ASLC design process and can also be used to facilitate the investigation of alternative ASLC architectures for the purpose of optimizing the performance of a specific sequential logic function. >

Control of Selective-Collective Elevators Based on the Use of Integrated Circuits

Selective-collective elevators present, as far as the logic design is concerned, the most complex control problems among simplex elevators. A control unit for this type of elevator, completely based on the use of digital integrated circuits, is described in the paper. The application of integrated circuits improves, in the authors' opinion, reliability and maintainability of elevator control as compared with the classical control units equipped with electromechanical relays and even more recent static solutions with discrete transistor logic circuits. This approach gives not only technical advantages, but is also justified from the economic point of view. The developed elevator control has been constructed and tested successfully on a six-floor office building. Owing to the conception of the functional subunits, it is possible to build up controls for any number of floors using only five standard printed circuit boards. The design of the control unit is based on the combinational and asynchronous sequential logic circuits. The Boolean equations, according to which the subunits were implemented, are given in the paper.

A Heuristic Algorithm for the Testing of Asynchronous Circuits

This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.