Asynchronous Microprocessor Research Articles

A Novel approach for Asynchronous Microprocessor Design and its Implementation on FPGA

The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper presents processor architecture design, its implementation followed by processor instruction set, data path flow for fetching unit, Register type, I-type and load /store type instruction flow. Thereafter this paper illustrates control unit design of processor that shows the controlling of signals for different units in processor design. Further, a complete internal structure is shown followed by features of novel processor architecture. It has capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.In the end, results have been shown using implementation windows. The complete design has been written using VHDL and then simulated and synthesized by XILINX ISE tool.

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.

An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM

This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route Placed design.

Design and Implementation of control Unit-ALU of 32 Bit Asynchronous Microprocessor based on FPGA

Design and Implementation of control Unit-ALU of 32 Bit Asynchronous Microprocessor based on FPGA

Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA

Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA

Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices

2015 Abstract This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronousreconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction,and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of themicroprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of theasynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralizedgenerator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This workcompares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Bothcircuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against1.6 MIPS for the synchronous.All Rights Reserved © 2015 Universidad Nacional Autonoma de Mexico, Centro de Ciencias Aplicadas y Desarrollo Tecnologico. This is anopen access item distributed under the Creative Commons CC License BY-NC-ND 4.0.

Research on Integration Degree Curve of Asynchronous Microprocessing Based on Virtual Characteristics Computing

Based on the virtual computing principle of computers feature and compatible MCU logic unit of full asynchronous microprocessor, this paper designs computer simulation platform of ideological and political education. The platform has data mining and analysis module. In order to verify the reliability of the platform, we design the data analysis simulation experiment of ideological and political education. Through the calculation, we can get the MCU integration curve. According to the impact of ideological and political education on users, we use computational analysis module to draw thinking fluctuation curve of political ideological education. We also can get thinking step characteristics of Political and ideological education which has high reference value for the research of the ideological and political education.

Design of an Asynchronous Microprocessor Using RSFQ-AT

Ultra-high speed microprocessors, clocked at hundreds of Gigahertz, remain the dreams of processor designers and consumers alike. However, such processors would require designs and clocking schemes that differ radically from that of current processors. This paper discusses superconductive asynchronous processors as one alternative to mainstream processors. This asynchronous design approach requires no global clocking, which reduces the complexity of global clock distribution, clock skew and considerations for clock jitter. The design of a 4-bit asynchronous microprocessor with a simple pipeline is covered. RSFQ-AT logic and its design methodology is used, and it is shown to be well suited to large scale asynchronous circuits. We show how the RSFQ-AT design methodology simplifies and speeds up the design process. Methods for performance evaluation of this asynchronous RSFQ microprocessor is also proposed.

43.1: A Flexible 8-bit Asynchronous Microprocessor Based on Low-Temperature Poly-Silicon (LTPS) TFT Technology

A flexible 8-bit asynchronous microprocessor based on low-temperature poly-silicon (LTPS) TFT technology, surface free technology by laser annealing and ablation (SUFTLA) and asynchronous circuit description language Verilog+ is presented. The 32k-transistor microprocessor consumes 180μA running at 500KHz, 5V. The power level is 30% of the synchronous counterpart.

Modeling an Asynchronous Microprocessor

Synchronous very large-scale integration (VLSI) design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Recently, there has been a resurgence of interest in asynchronous design techniques due to the significant potential benefits that the elimination of global synchronization may offer to issues such as clock distribution, power consumption, performance, and modularity. Modeling and simulation may perform a catalytic role in the quest for the realization of the potential offered by asynchronous logic. Hence, the recurrence of interest in asynchronous design has been accompanied by intense research activity aimed at developing notations and techniques appropriate for modeling and simulating asynchronous systems. Communication sequential processes and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This article discusses the modeling of an asynchronous microprocessor using occam.

An asynchronous copy-back cache architecture

Over the past 10 years asynchronous design has re-emerged as a viable alternative to clocked design with mounting evidence of competitive performance, power efficiency and electromagnetic compatibility compared to the more mainstream synchronous style. This paper presents an asynchronous cache architecture—the logical choice for use with an asynchronous microprocessor where a synchronous cache compromises the asynchronous benefits of the processor. The design presented here provides the processor with a unified, dual-ported view of its memory subsystem using multiple interleaved blocks. Each block has separate instruction and data line-buffers acting as level-zero (L0) cache making cache access time highly variable. The cache employs a copy-back write strategy to support a high-performance embedded processor core. The design is optimised for the Amulet3 microprocessor core, the third fully asynchronous implementation of the ARM architecture, but the techniques employed are generally applicable to any asynchronous processor.

Simulating asynchronous hardware on multiprocessor platforms: the case of AMULET1

AbstractSynchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques which promise to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra communicating sequential processes (CSP) and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This paper focuses on issues related to the execution of CSP/occam models of asynchronous hardware on multiprocessor machines, including I/O, monitoring and debugging, partition, mapping and load balancing. These issues are addressed in the context of occarm, an occam simulation model of the AMULET1 asynchronous microprocessor; however, the solutions devised are more general and may be applied to other systems too. Copyright © 2001 John Wiley & Sons, Ltd.

Synthesising an asynchronous DMA controller with Balsa

A DMA controller has been designed and implemented as part of the AMULET3i asynchronous microprocessor macrocell using a mixture of synchronous and asynchronous circuit techniques. The synthesis language Balsa has been used to implement the major part of the controller, the asynchronous control. The use of Balsa has allowed the controller to be rapidly re-engineered in response to a changing specification.

MARBLE: an asynchronous on-chip macrocell bus

This paper presents MARBLE, the Manchester Asynchronous Bus for Low Energy, a two channel asynchronous micropipeline-style VLSI macrocell bus. In addition to basic bus functions, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a practical, fully asynchronous design style. MARBLE is used in the AMULET3i asynchronous Microprocessor system to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data-cycles with a protocol based on split-transfers to meet the performance needs of such a system.

Asynchronous microprocessors: From high level model to FPGA implementation

Abstract Asynchronous logic principles can be potentially advantageous for novel micro-processor designs as they offer greater design modularity and complete avoidance of clock distribution, mitigate various negative operational effects such as metastability, high power dissipation and electromagnetic emission, to name but a few. The designs of the Amulet microprocessors, originally built as an asynchronous “challenge” to the clocked ARM architecture, have already demonstrated that some of these benefits can be realised in practice. As more asynchronous processor designs are expected within the next decade, the problem of an efficient design methodology is of prime importance. We present an FPGA implementation of an asynchronous microprocessor, called ADLX. This microprocessor employs 2-phase event driven transition signalling logic that functions within the conceptual framework of a Sutherland micropipeline. The implementation was constructed from a series of VHDL descriptions using a range of commercially available products. Parts of the design were developed using Petri Net models which were validated and then synthesized using Petrify, a software tool designed for the manipulation of concurrent specifications of asynchronous control circuits.

Asynchronous processor survey

Virtually all computers today are synchronous. As systems grow increasingly large and complex the clock can cause big problems with clock skew, a timing delay that can create havoc with the overall design. It can also increase the circuit silicon and power dissipation, which can affect overheating and power supplies. Computer architecture researchers are actively considering asynchronous processor design. Asynchronous architectures permit modular design. Each subsystem or functional block can be optimized without being synchronized to a global clock, which simplifies interfacing. Moreover, an asynchronous system exhibits the average performance of all the individual components, rather than the synchronous system's worst-case performance of a single component. Furthermore, asynchronous processors may yet prove to offer reduced power dissipation by inherently shutting down unused portions of the circuit. This article examines the key architecture issues that concern designers and compares six developmental asynchronous architectures: CAP, the Caltoch Asynchronous Processor; FAM, the Fully Asynchronous Microprocessor; NSR, the Nonsynchronous RISC; CFPP, the Counterflow Pipeline Processor; Strip, a Self-Assured RISC Processor; and Amulet 1.

Superscalar instruction issue in an asynchronous microprocessor

The implementation of the instruction issuer for a superscalar asynchronous microprocessor (SCALP) is described as a case study in asynchronous design. The issuer accepts five instructions at a time from the memory interface and issues them out of order to five parallel functional units. SCALP's architecture is designed to reduce the complexity of the instruction issuer by removing the need to detect dependencies between instructions as they are issued. The design has a regular cellular structure suitable for VLSI implementation. The issue's performance is sufficient that no bottleneck forms in the SCALP pipeline.

A 100-MIPS GaAs asynchronous microprocessor

The authors describe how they ported an asynchronous microprocessor previously implemented in CMOS to gallium arsenide, using a technology-independent asynchronous design technique. They introduce new circuits including a sense-amplifier, a completion detection circuit, and a general circuit structure for operators specified by production rules. The authors used and tested these circuits in a variety of designs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The first asynchronous microprocessor: the test results

We have designed the first entirely asynchronous (also called self-timed or delay-insensitive) microprocessor. The design was reported at the Decennial Caltech Conference on VLSI, last March. The conference paper is included here as an appendix. Since the chips had not yet been fabricated at the moment of writing the conference paper, the paper does not include the results of the experiment. The purpose of this note is to publish these results, which are quite remarkable because of the speed reached on this first design, and, as importantly, because of the surprising robustness of the chips to variations in temperature and VDD voltage values.

The design of an asynchronous microprocessor

Abstract : Prejudices are as tenacious in science and engineering as in any other human activity. One of the most firmly held prejudices in digital VLSI design is that asynchronous circuits-a.k.a. self-timed or delay-insensitive circuits-are necessarily slow and wasteful in area and logic. Whereas asynchronous techniques would be appropriate for control, they would be inadequate for data paths because of the cost of dual-rail encoding of data, the cost of generating completion signals for write operations on registers, and the difficulty of designing self-timed buses. Because a general-purpose microprocessor contains a complex data path, a corollary of the previous opinion is that it is impossible to design an efficient asynchronous microprocessor. Since we have been developing a design method for asynchronous circuits that gives excellent results, and since the above objections to large-scale data path designs are genuine but untested, we decided to pick up the gauntlet and design a complete processor. The design of an asynchronous microprocessor poses new challenges and opens new avenues to the computer architect. Hence, the experiment unavoidably developed a dual purpose: We are refining an already well-tested design method and we are starting a new series of experiments in asynchronous architectures. (As far as we know, this is the first entirely asynchronous microprocessor ever built.) The results we are reporting have a different implication depending on whether they are related to the first or second goal of the experiment. Whereas we are convinced that our design methods have reached maturity, we are quite aware that asynchronous techniques may influence the computer architects in completely new ways that this first design is just starting to explore.