Asynchronous Interface Research Articles

Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks

AbstractTo expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full‐custom approach in a 28‐nm CMOS (complementary metal–oxide–semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.

Hardware circuit implementation of transmitter and receiver based on UART protocol

In today's information age, the amount of data as an important information carrier is growing at an explosive rate. The importance of its transmission rate, stability, accuracy and other properties is gradually becoming more and more important. UART as a communication protocol is widely used in embedded and IoT systems. It is simpler and more direct than SP2 and I2C, which can greatly simplify the complexity of digital circuits and become one of the key directions to improve the performance of data transmission. In this paper, a digital circuit based on the transmitter and receiver side of the UART protocol has been constructed using the hardware description language of Verilog HDL to implement the function of receiving and transmitting data based on a clock signal of 50 MHz and a baud rate of 115200 bps as well as the use of an RS232 asynchronous serial interface. The simulation was carried out using Quartus II.

Lamarckian Platform: Pushing the Boundaries of Evolutionary Reinforcement Learning Toward Asynchronous Commercial Games

Despite the emerging progress of integrating evolutionary computation into reinforcement learning, the absence of a high-performance platform endowing composability and massive parallelism causes non-trivial difficulties for research and applications related to asynchronous commercial games. Here we introduce Lamarckian <xref ref-type="fn" rid="fn1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">¹</xref> <fn id="fn1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><label>¹</label> The code and demonstrational setup of Lamarckian are publicly available at <uri>https://github. com/lamarckian/lamarckian</uri>. </fn> – an open-source platform featuring support for evolutionary reinforcement learning scalable to distributed computing resources. To improve the training speed and data efficiency, Lamarckian adopts optimized communication methods and an asynchronous evolutionary reinforcement learning workflow. To meet the demand for an asynchronous interface by commercial games and various methods, Lamarckian tailors an asynchronous Markov Decision Process interface and designs an object-oriented software architecture with decoupled modules. In comparison with the state-of-the-art RLlib, we empirically demonstrate the unique advantages of Lamarckian on benchmark tests with up to 6000 CPU cores: i) both the sampling efficiency and training speed are doubled when running PPO on Google football game; ii) the training speed is 13 times faster when running PBT+PPO on Pong game. Moreover, we also present two use cases: i) how Lamarckian is applied to generating behavior-diverse game AI; ii) how Lamarckian is applied to game balancing tests for an asynchronous commercial game.

A Wearable Asynchronous Brain-Computer Interface Based on EEG-EOG Signals With Fewer Channels.

Brain-computer interfaces (BCIs) have tremendous application potential in communication, mechatronic control and rehabilitation. However, existing BCI systems are bulky, expensive and require laborious preparation before use. This study proposes a practical and user-friendly BCI system without compromising performance. A hybrid asynchronous BCI system was developed based on an elaborately designed wearable electroencephalography (EEG) amplifier that is compact, easy to use and offers a high signal-to-noise ratio (SNR). The wearable BCI system can detect P300 signals by processing EEG signals from three channels and operates asynchronously by integrating blink detection. The wearable EEG amplifier obtains high quality EEG signals and introduces preprocessing capabilities to BCI systems. The wearable BCI system achieves an average accuracy of 94.03±4.65%, an average information transfer rate (ITR) of 31.42±7.39 bits/min and an average false-positive rate (FPR) of 1.78%. The experimental results demonstrate the feasibility and practicality of the developed wearable EEG amplifier and BCI system. Wearable asynchronous BCI systems with fewer channels are possible, indicating that BCI applications can be transferred from the laboratory to real-world scenarios.

SPI Master Slave Communication

The serial-peripheral interface (SPI) protocol also called asynchronous serial interface specification is used for communication between single master and single/multiple slaves. With the increase in number of slaves causing high complexity of circuit creates a demand in self-test ability feature for SPI module in order to test for fault free circuits. Built-In-Self-Test (BIST) in the answer for self-test in circuits as well as it helps in reduction of maintenance and testing cost. Design of BIST embedded SPI module with single master and single slave configuration has been introduced in these paper, Here 8-bit is transferred across the module, Where the Circuit under Test (CUT) is being Self-Tested with BIST feature for its correctness. This SPI module is designed using Verilog hardware description language(HDL) using EDA playground platform for application like applications specific integrated circuit (ASIC) or system on chip (SOC). SPI stands for the Serial Peripheral Interface. It is a serial communication protocol that is used to connect low-speed devices. It was developed by Motorola in the mid-1980 for inter-chip communication. It is commonly used for communication with flash memory, sensors, real-time clock (RTC), analog-to-digital converters, and more. It is a full-duplex synchronous serial communication, which means that data can be simultaneously transmitted from both directions. The main advantage of the SPI is to transfer the data without any interruption. Many bits can be sent or received at a time in this protocol. In this protocol, devices are communicated in the master-slave relationship. The master device controls the slave device, and the slave device takes the instruction from the master device. The simplest configuration of the Serial Peripheral Interface (SPI) is a combination of a single slave and a single master. But, one master device can control multiple slave devices

A Novel Asynchronous Brain Signals-Based Driver-Vehicle Interface for Brain-Controlled Vehicles.

Directly applying brain signals to operate a mobile manned platform, such as a vehicle, may help people with neuromuscular disorders regain their driving ability. In this paper, we developed a novel electroencephalogram (EEG) signal-based driver-vehicle interface (DVI) for the continuous and asynchronous control of brain-controlled vehicles. The proposed DVI consists of the user interface, the command decoding algorithm, and the control model. The user interface is designed to present the control commands and induce the corresponding brain patterns. The command decoding algorithm is developed to decode the control command. The control model is built to convert the decoded commands to control signals. Offline experimental results show that the developed DVI can generate a motion control command with an accuracy of 83.59% and a detection time of about 2 s, while it has a recognition accuracy of 90.06% in idle states. A real-time brain-controlled simulated vehicle based on the DVI was developed and tested on a U-turn road. Experimental results show the feasibility of the DVI for continuously and asynchronously controlling a vehicle. This work not only advances the research on brain-controlled vehicles but also provides valuable insights into driver-vehicle interfaces, multimodal interaction, and intelligent vehicles.

A Hybrid Method Fusing Frequency Recognition With Attention Detection to Enhance an Asynchronous Brain-Computer Interface.

One critical problem in controlling an asynchronous brain-computer interface (BCI) system is to discriminate between control and idle states. This paper proposes a hybrid attention detection and frequency recognition method based on weighted Dempster-Shafer theory (ADFR-DS), which integrates information of different aspects of the task from two brain regions, to enhance asynchronous control performance of a steady-state visual evoked potential (SSVEP)-based BCI system. The ADFR-DS method utilizes a hybrid architecture to process electroencephalogram (EEG) data from different channels simultaneously: an individualized frequency band based optimized complex network (IFBOCN) algorithm processes neural activity from the prefrontal area for attention detection, and an ensemble task-related component analysis (eTRCA) algorithm processes data from the occipital area for frequency recognition. The ADFR-DS method then fuses their classification results at decision level to generate the final output of the BCI system. A novel weighted Dempster-Shafer fusion method was proposed to enhance the fusion performance. This study evaluated the proposed method using a 40-target dataset recorded from 35 participants. The proposed method outperformed the eTRCA algorithm in the true positive rate (TPR), true negative rate (TNR), accuracy (ACC) and information transfer rate (ITR). Specifically, ADFR-DS improved the average ACC of eTRCA from 62.71% to 69.30%, and improved the average ITR from 184.28 bits/min to 216.89 bits/min (data length 0.3 s). The results suggest that the proposed ADFR-DS method can enhance asynchronous SSVEP-based BCI systems.

A Custom Parallel Hardware Architecture of Nonlinear Model-Predictive Control on FPGA

This article presents the field-programmable gate array (FPGA) implementation of a particle swarm optimization (PSO)-based nonlinear model-predictive control (NMPC) for applications with millisecond timescales and resource-constrained embedded systems. A custom hardware circuit architecture of an NMPC controller, which mainly includes phase-locked loop clock, universal asynchronous receiver transmitter interface, trigonometric function, random number generator, objective function, and PSO solver modules, is implemented on the FPGA based on a hardware description language specification. It employs parallelism, pipelining, and specialized numerical formats to enhance the online computation performance of NMPC. In addition, the partial parallel expansion calculations of the fitness (objective) function and the particle position update are adopted for trading off the computational performance against resource usage. The hardware-in-the-loop experimental results through controlling a wheeled mobile robot model demonstrate that the design is capable of computing the required control action in real time by using a midrange FPGA, while still offering good control performance.

Synthesis of the control system for the positioning pneumatic drive of shut-off fittings according to the criteria of technological efficiency

This paper reports the new design of an experimental bench to study the effectiveness of the positional drive control system of shut-off fittings. For research, the operating modes of the disk flap and ball valve, based on proportional elements with feedback (4–20 mA), were programmatically formed and described. The mathematical model of control over shut-off devices has been analytically described on the example of a disk rotary valve with the possibility of further analysis of individual stages in accordance with the accepted assumptions. The operating control signal is justified with a serial asynchronous interface with an offset operating range of permissible values of –16.0 mA. Separate stages in the operation of the synthesized shut-off fittings based on accepted assumptions have been described. Measurements were performed for disc damper angles of 30°, 60°, 90° by variable value of the pressure control signal (1...4 bar) with sampling of measuring indicators for the control system in real time. The results obtained experimentally confirmed the adequacy of numerical modeling regarding the study of the disk rotary inter-flange valve, as well as preliminary assumptions in the mathematical model. Data were obtained to test the efficiency of controlled shut-off fittings (V-shaped ball valve, disc rotary inter-flange valve) at a sugar factory. The average angle of rotation for a ball is 17.61 degrees; the average value of the vapor temperature after cooling is 130.91 °C (subject to a given value of 130.0 °C). The deviation of the set value is 0.7 %. The average value for the angle of rotation of the disc damper at 43.0 degrees showed the largest deviation of technological parameters of 1.45 %.

Designing Asynchronous Online Discussion Forum Interface and Interaction Based on the Community of Inquiry Framework

The community of inquiry (CoI) framework describes a process for creating collaborative learning through three elements or presences: social, cognitive, and teaching. Despite its popularity among researchers and practitioners, use of the CoI model is limited to mapping instructional activities, which are yet to be developed into an interaction design for online collaborative learning intended to support the CoI presences. This study was aimed at developing the interaction design of an asynchronous online discussion forum employing a user-centered design method contextualized to the learning-centered design approach. Seven scenario and user interfaces were created to facilitate one introductory activity and four phases of inquiry. The design was evaluated through contextual interviews with ten students. The interviews revealed that the prototype encouraged and supported (a) introductory activity (social presence), (b) idea exploration (cognitive presence), (c) summarizing the discussion (cognitive presence), and (d) facilitating discussion (teaching presence). Future research could be aimed at improving the proposed design based on recommendations and developing a fully functional working system to be tested in real settings.

A fisher linear discriminant analysis classifier fused with naïve Bayes for simultaneous detection in an asynchronous brain-computer interface

BackgroundAn asynchronous event-related potential-based brain computer interface (ERP-BCI) permits the subjects to output intentions at their own pace, which provides a more free and practical communication pathways without the need for muscle activity. The core of constructing this type of system is to discriminate both the intentions and brain states. New methodsThis study proposes a fisher linear discriminant analysis classification algorithm fused with naïve Bayes (B-FLDA) for the ERP-BCI to simultaneous recognize the subjects’ intentions, working and idle states. This method uses the spectral characteristics of visual-evoked potential and the time-domain characteristics of ERP to simultaneously detect brain states and target stimulus, and obtain the final discrimination result through probability fusion. ResultsThe accuracy and the information transfer rate increase to 98.61% and 62.80 bits/min under 10 repetitions and 1 repetition, respectively. The three parameters of receiver operator characteristic curve have achieved better performance. Comparison with existing methodsTen subjects participate in this study with the proposed algorithms and two other control methods. The accuracy and information transfer rate of this algorithm are better than the other methods. ConclusionsIt indicates that the naïve Bayes-FLDA algorithm is able to improve the performance of an asynchronous BCI system by detecting the intentions and states simultaneously.

Asynchronous RPC Interface in Distributed Computing System

Asynchronous RPC Interface in Distributed Computing System

Design of UAV Flight Control System

In order to improve the control performance of UAV. For a small UAV, the hardware design scheme of UAV flight control computer with STM32 as the processing core is proposed and implemented. The overall scheme design, specific hardware selection and interface design of the system are given in detail. STM32, as the main controller, expands the parallel A/D, D/A, asynchronous serial communication interface and memory around, enriches the system hardware interface resources, and selects the peripheral expansion circuit with complex programmable logic controller (CPID) to realize interrupt control. This flight control computer has the characteristics of small volume and strong autonomous navigation ability.

Automatic migration from synchronous to asynchronous JavaScript APIs

The JavaScript ecosystem provides equivalent synchronous and asynchronous Application Programming Interfaces (APIs) for many commonly used I/O operations. Synchronous APIs involve straightforward sequential control flow that makes them easy to use and understand, but their "blocking" behavior may result in poor responsiveness or performance. Asynchronous APIs impose a higher syntactic burden that relies on callbacks, promises, and higher-order functions. On the other hand, their nonblocking behavior enables applications to scale better and remain responsive while I/O requests are being processed. While it is generally understood that asynchronous APIs have better performance characteristics, many applications still rely on synchronous APIs. In this paper, we present a refactoring technique for assisting programmers with the migration from synchronous to asynchronous APIs. The technique relies on static analysis to determine where calls to synchronous API functions can be replaced with their asynchronous counterparts, relying on JavaScript's async/await feature to minimize disruption to the source code. Since the static analysis is potentially unsound, the proposed refactorings are presented as suggestions that must be reviewed and confirmed by the programmer. The technique was implemented in a tool named Desynchronizer. In an empirical evaluation on 12 subject applications containing 316 synchronous API calls, Desynchronizer identified 256 of these as candidates for refactoring. Of these candidates, 244 were transformed successfully, and only 12 resulted in behavioral changes. Further inspection of these cases revealed that the majority of these issues can be attributed to unsoundness in the call graph.

Design and Innovation of Asynchronous Serial Communication Interface Conversion System of Field Bus

Since the traditional asynchronous serial communication interface conversion system has a series of problems in data reliability, CPU utilization and so on, this paper, starting from the design idea of fieldbus, uses CAN, PROFIBUS-DP, power conversion module, core control module and other software programs to study the conversion process, so as to innovate the conversion system and realize the reliability of data, which greatly improves the utilization rate of CPU.

Enhanced Performance of a Brain Switch by Simultaneous Use of EEG and NIRS Data for Asynchronous Brain-Computer Interface.

Previous studies have shown the superior performance of hybrid electroencephalography (EEG)/ near-infrared spectroscopy (NIRS) brain-computer interfaces (BCIs). However, it has been veiled whether the use of a hybrid EEG/NIRS modality can provide better performance for a brain switch that can detect the onset of the intention to turn on a BCI. In this study, we developed such a hybrid EEG/NIRS brain switch and compared its performance with single modality EEG- and NIRS-based brain switch respectively, in terms of true positive rate (TPR), false positive rate (FPR), onset detection time (ODT), and information transfer rate (ITR). In an offline analysis, the performance of a hybrid EEG/NIRS brain switch was significantly improved over that of EEG- and NIRS-based brain switches in general, and in particular a significantly lower FPR was observed for the hybrid EEG/NIRS brain switch. A pseudo-online analysis was additionally performed to confirm the feasibility of implementing an online BCI system with our hybrid EEG/NIRS brain switch. The overall trend of pseudo-online analysis results generally coincided with that of the offline analysis results. No significant difference in all performance measures was also found between offline and pseudo online analysis schemes when the amount of training data was same, with one exception for the ITRs of an EEG brain switch. These offline and pseudo-online results demonstrate that a hybrid EEG/NIRS brain switch can be used to provide a better onset detection performance than that of a single neuroimaging modality.

Recognition of the idle state based on a novel IFB-OCN method for an asynchronous brain-computer interface

BackgroundA major difficulty for the asynchronous brain-computer interface (BCI) lies in the accurate recognition of the control and idle states. Although subject’s attention level was found to be different in these states, the validity of recognizing them using attention features has not been studied. New methodsThis paper proposed a novel Individualized Frequency Band based Optimized Complex Network (IFB-OCN) method to enhance the performance of discriminating the control and idle states. The IFB-OCN method extracted the attention features from a single FPz channel, selected the first three individualized frequency bands with the highest accuracies, and integrated the features of these bands for classification. ResultsThe performance was evaluated using a steady-state visual evoked potential (SSVEP)-based BCI task. In the offline evaluation, the IFB-OCN method achieved the highest average accuracy of 93.5 % with the data length of 4 s, and achieved the highest information transfer rate (ITR) of 47.3 bits/min with the data length of 0.5 s. In the simulated online evaluation, the IFB-OCN method obtained a true positive rate (TPR) of 89.8 % and a true negative rate (TNR) of 86.2 %. Comparison with existing methodsThe proposed IFB-OCN method recognized the control and idle states using a single FPz channel rather than the occipital channels, and outperformed the existing algorithms in the accuracy of detecting the attention level. ConclusionsThese results demonstrate that the proposed IFB-OCN method is efficient in recognizing the idle state and has a great potential for enhancing the asynchronous BCIs.

Influential Factors of an Asynchronous BCI for Movement Intention Detection.

In recent years, asynchronous brain computer interface (BCI) systems have been utilized in many domains such as robot controlling, assistive technology, and rehabilitation. In such BCI systems, movement intention detection algorithms are used to detect movement desires. In recent years, movement-related cortical potential (MRCP), an electroencephalogram (EEG) pattern representing voluntary movement intention, attracts wide attention in movement intention detection. Unfortunately, low MRCP detection accuracy makes the asynchronous BCI system impractical for real usage. In order to develop an effective MRCP detection algorithm, EEG data have to be properly preprocessed. In this work, we investigate the relationship and effects of three factors including frequency bands, spatial filters, and classifiers on MRCP classification performance to determine best settings. In particular, we performed a systematic performance investigation on combinations of five frequency bands, five spatial filters, and six classifiers. The EEG data were acquired from subjects performing series of self-paced ankle dorsiflexions. Analysis of variance (ANOVA) statistical test was performed on F1 scores to investigate effects of these three factors. The results show that frequency bands and spatial filters depend on each other. The combinations directly affect the F1 scores, so they have to be chosen carefully. The results can be used as guidelines for BCI researchers to effectively design a preprocessing method for an advanced asynchronous BCI system, which can assist the stroke rehabilitation.

An idle state-detecting method based on transient visual evoked potentials for an asynchronous ERP-based BCI

BackgroundAn asynchronous brain-computer interface (BCI) allows subject to freely switch between the working state and the idle state, improving the subject’s comfort. However, using only the event-related potential (ERP) to detect these two states is difficult because of the small amplitude of the ERP. MethodOur previous study finds that an odd-ball paradigm could evoke transient visual evoked potentials (TSVEPs) simultaneously with ERPs. This study adopts the TSVEP and the ERP to detect the idle state in the design of an asynchronous TSVEP-ERP-based BCI (T-E BCI). The T-E BCI extracts time and frequency features from brain signals and uses a novel probability-based fisher linear discriminant analysis (P-FLDA) to combine the classification results of the ERP and the TSVEP. ResultTen subjects perform visual speller and video watching experiments, and their brain signals are measured under the working and idle states. The main results show that the T-E BCI achieves a higher accuracy than the ERP-based BCI when judging the subject’s intentions and the two states. The P-FLDA performs better than the FLDA in combining the classification results. ConclusionsThe study demonstrates that adding the TSVEP can substantially reduce the number of wrongly detected trials. The T-E BCI provides a new way of designing an asynchronous BCI without adding any additional visual stimuli, which makes the BCI more practical.

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study.

Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.