Asynchronous Design Methods Research Articles

A Methodology to Design Static NCL Libraries

The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.

NCL 기반의 저전력 ALU 회로 설계 및 구현

저전력 설계를 요구하는 디지털 시스템에서는 동적 전력(dynamic power)과 누설 전력(leakage power) 사이의 균형을 이루는 점에 근접하는 매우 낮은 전압에서 작동하는 디지털 설계 방식을 요구하지만, 기존의 동기방식의 회로는 낮은 전압에서 지연(delay)이 급격히 증가하여 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라, 공정, 전압, 온도 변이 (PVT variation) 등에 크게 영향을 받아서 올바른 동작을 기대할 수 없다. 따라서 본 논문에서는 낮은 전압에서 여러 가지 변이들에 영향을 받지 않는 비동기회로 설계 방식 중에 타이밍 분석이 요구되지 않고, 설계가 간단한 NCL (Null Convention Logic) 방식을 사용한 저전력 산술논리 연산장치 (ALU) 회로를 매그나칩-SK하이닉스 0.18um 공정으로 설계하고, 기존의 파이프라인 방식의 ALU와 스피드와 전력에 관해서 비교하였다. Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

Event-driven logic (EDL) approach to digital systems representation and related design processes

There is a well established and growing need for fast digital processors and fast digital systems generally in many areas of application. In the design of sequential logic in particular, the problems of clock skew and the fact that the clock period is essentially determined by the speed of the slowest parts of the system are significant limiting factors. Consequently, attention is turning to asynchronous, self-timing, systems to provide a way of achieving extra speed in time-critical applications. Designers may well argue that asynchronous circuitry is difficult to design and prone to all sorts of hazards and potential instability problems but, on the other hand, the clock distribution layout of very fast synchronous systems is also quite difficult to design and simulate. Traditional asynchronous design methods are, in the opinion of the author, quite cumbersome and often difficult to use. Attention is therefore turning to ways of improving asynchronous circuit representation and design processes. An alternative way of approaching the representation and design of asynchronous sequential systems is to take an ‘event-driven logic (EDL)’ or ‘transition-based’ approach. In concept, the approach taken is to define the initial conditions of a system in terms of the logic level assumed by each variable and then to describe subsequent system behaviour in terms of the transitions (changes in logic level, also called events) of those variables. The paper pursues this approach, making use of special operators and introducing appropriate EDL functions and design processes.