Asymmetric Multicore Processors Research Articles

Scheduling Garbage Collection for Energy Efficiency on Asymmetric Multicore Processors

Scheduling Garbage Collection for Energy Efficiency on Asymmetric Multicore Processors

A BSF‐EDZL scheduling algorithm for heterogeneous multiprocessors

AbstractTo improve the performance of real‐time systems, heterogeneous asymmetric multiprocessors are proposed. Heterogeneous asymmetric multiprocessor architecture allows the system to better match computational resources to meet the needs and dynamic workload of each application. The benefits of system performance and reduced power consumption cannot be fully exploited unless proper task scheduling and task allocation methods are implemented at the operating system level.The EDZL scheduling algorithm has been shown to be a better scheduling algorithm in heterogeneous multiprocessor platforms. In this paper, the BSF‐EDZL (best speed fit for earliest deadline first until zero‐laxity) performance asymmetric multiprocessor scheduling algorithm is proposed, and an effective schedulability analysis is performed. The algorithm selects an appropriate processor for non‐zero relaxation highest priority task rather than the fastest processor when assigning tasks. Experimental results show that the proposed BSF‐EDZL scheduling algorithm can schedule a larger set of tasks than the ordinary EDZL scheduling algorithm.

Energy-Efficient Federated Training on Mobile Device

On-device deep learning technology has attracted increasing interest recently. CPUs are the most common commercial hardware on devices and many training libraries have been developed and optimized for them. However, CPUs still suffer from poor training performance (i.e., training time) due to the specific asymmetric multiprocessor. Moreover, the energy constraint imposes restrictions on battery-powered devices. With federated training, we expect the local training to be completed rapidly therefore the global model converges fast. At the same time, energy consumption should be minimized to avoid compromising the user experience. To this end, we consider energy and training time and propose a novel framework with a machine learning-based adaptive configuration allocation strategy, which chooses optimal configuration combinations for efficient ondevice training. We carry out experiments on the popular library MNN and the experimental results show that the adaptive allocation algorithm reduces substantial energy consumption, compared to all batches with fixed configurations on off-the-shelf CPUs.

Priority Based Scheduler for Asymmetric Multi-core Edge Computing

Edge computing technology has gained popularity due to its ability to process data near the source or collection device, benefiting from low bandwidth utilization and enhanced security. Edge devices are typically equipped with multiple devices that employ asymmetric multi-cores for efficient data processing. To ensure optimal performance, it is crucial to carefully assign tasks to the appropriate cores in asymmetric multi-core processors. However, the current Linux scheduler needs to consider the capabilities of individual cores when assigning tasks. Consequently, high-priority tasks may be assigned to energy-efficient cores, while low-priority tasks end up on high-performance cores. This sub-optimal task assignment negatively impacts the overall system performance. To address this issue, a new algorithm has been proposed. This algorithm considers both the core’s capabilities and the task’s priority. However, due to the asymmetric nature of the cores, prior knowledge of each core’s speed is necessary. The algorithm fetches the priorities of the tasks and classifies them into high, medium, and low-priority categories. High-priority tasks are scheduled on high-performance cores, while medium and low-priority tasks are allocated to energy-efficient cores. The proposed algorithm demonstrates superior performance for high-priority tasks compared to the existing Linux task scheduling algorithm. It significantly improves task scheduling time by up to 16%, thereby enhancing the system’s overall efficiency.

Three Processor Allocation Approaches towards EDF Scheduling for Performance Asymmetric Multiprocessors

With the rapid development of high-performance computing and parallel computing technology, by virtue of its cost-effectiveness, strong scalability, and easy programming, the multiprocessor system has gradually become the mainstream computing platform. Meanwhile, a growing number of researchers pay attention to the performance of multiprocessor systems, especially the task scheduling problem, which has an important impact on the system performance. Most of the current research works on task scheduling algorithms are based on the homogeneous computing environment. On the contrary, research works focusing on more complex performance asymmetric multiprocessor environments still remain rare. In this paper, we compare the effects of three earliest deadline first algorithms under different processor allocation strategies on performance asymmetric multiprocessors. We propose an efficient schedulability analysis for an allocation strategy that assigns high-priority tasks to the slowest idle processor. Experimental results show that the strategy of allocating processors with optimum speeds for high-priority tasks can schedule more task sets than the other two allocation strategies. The strategy that prioritizes the slowest processors for high-priority tasks has the smallest number of task migrations, and the strategy has the highest effective processor utilization.

Analyzing Nelder-Mead Simplicial Heuristic Using DEMATEL Method

Nelder-Mead Simplicial Heuristic in DEMATEL Method. A simple volume mesh element patterns a parallel algorithm framework for optimization we describe. By using simultaneous Parallel and asymmetric multiprocessing in hardware, we achieve more than this ten times the speed of Current state-of-the-art sequencing methods. Alternative: Strength ’pedestrian avoidance, For intimate and personal spaces moderation in between, For intimate and personal spaces The intensity of the transition between Strength of obstacle avoidance, Governs the queue width, Evaluation Preference: The strength of ’pedestrian avoidance (A1), Moderation between intimate and personal space (A2), The intensity of transition between intimate and personal space (A3), and Strength of obstacle avoidance(A4), Governs the queue width(A5), From the result it is seen that Strength of ’pedestrian avoidance and is got the first rank whereas is the Strength of obstacle avoidance got is having the lowest rank. The value of the dataset for Freight Distribution Concept Selection in DEMATEL shows that it results in Strength of ’pedestrian avoidance and top ranking.

System-on-chip single event effect hardening design and validation using proton irradiation

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

Towards hybrid supercomputing architectures

In light of recent work on combining control-flow and dataflow architectures on the same chip die, a new architecture based on an asymmetric multicore processor is proposed. The control-flow architectures are described as a most commonly used computer architecture today. Both multicore and manycore architectures are explained, as they are based on the same principles. A dataflow computing model assumes that data input flows through hardware as either a software or hardware dataflow implementation. In software dataflow, processors based on the control-flow paradigm process tasks based on their availability from the same queue (if there are any). In hardware dataflow architectures, the hardware is configured for a particular algorithm, and data input is streamed into the hardware, and the output is streamed back to the multicore processor for further processing. Hardware dataflow architectures are usually implemented with FPGAs. Hybrid architectures employ asymmetric multicore and manycore computer architectures that are based on the control-flow and hardware dataflow architecture, all combined on the same chip die. Advantages include faster processing time, lower power consumption (and heating), and less space needed for the hardware.

Dynamic Priority Real-Time Scheduling on Power Asymmetric Multicore Processors

The use of real-time systems is growing at an increasing rate. This raises the power efficiency as the main challenge for system designers. Power asymmetric multicore processors provide a power-efficient platform for building complex real-time systems. The utilization of this efficient platform can be further enhanced by adopting proficient scheduling policies. Unfortunately, the research on real-time scheduling of power asymmetric multicore processors is in its infancy. In this research, we have addressed this problem and added new results. We have proposed a dynamic-priority semi-partitioned algorithm named: Earliest-Deadline First with C=D Task Splitting (EDFwC=D-TS) for scheduling real-time applications on power asymmetric multicore processors. EDFwC=D-TS outclasses its counterparts in terms of system utilization. The simulation results show that EDFwC=D-TS schedules up to 67% more tasks with heavy workloads. Furthermore, it improves the processor utilization up to 11% and on average uses 14% less cores to schedule the given workload.

Capability Aware Dynamic Load Balancer for Asymmetric NUMA Multicore Processors

Capability Aware Dynamic Load Balancer for Asymmetric NUMA Multicore Processors

Collaborative Heterogeneity-Aware OS Scheduler for Asymmetric Multicore Processors

Asymmetric multicore processors (AMP) offer multiple types of cores under the same programming interface. Extracting the full potential of AMPs requires intelligent scheduling decisions, matching each thread with the right kind of core, the core that will maximize performance or minimize wasted energy for this thread. Existing OS schedulers are not up to this task. While they may handle certain aspects of asymmetry in the system, none can handle all runtime factors affecting AMPs for the general case of multi-threaded multi-programmed workloads. We address this problem by introducing COLAB, a general purpose asymmetry-aware scheduler targeting multi-threaded multi-programmed workloads. It estimates the performance and power of each thread on each type of core and identifies communication patterns and bottleneck threads. With this information, the scheduler makes coordinated core assignment and thread selection decisions that still provide each application its fair share of the processor's time. We evaluate our approach using both the GEM5 simulator on four distinct big.LITTLE configurations and a development board with ARM Cortex-A73/A53 processors and mixed workloads composed of PARSEC and SPLASH2 benchmarks. Compared to the state-of-the art Linux CFS and AMP-aware schedulers, we demonstrate performance gains of up to 25 and 5 to 15 percent on average, together with an average 5 percent energy saving depending on the hardware setup.

Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid putting additional burden on a programmer. Therefore, the proposed solution should be fully implemented in hardware. In the asymmetric multiprocessor that is analyzed, all cores have the same instruction set, but they are asymmetric in terms of microarchitectural properties, so that N −1 “small” cores are identical, while the $\text{N}^{\mathrm {th}}$ “big” core is different, as it provides better performance and higher capacities of its units. The idea is to perform transaction migration from the “small” core to the “big” one, based on the history of transaction execution. The experiments were performed using a significantly upgraded Gem5 simulator and eight parallel applications from the STAMP benchmark suite. The experimental results show the speedup and the rate of successfully executed transactions for five different multiprocessor configurations, including symmetric and asymmetric multiprocessors with or without transaction migration. The improvement our algorithm achieves for suitable applications is up to 14% (10% on average) in turnaround time compared to the solutions which do not make use of asymmetry for scheduling transactions.

NileOS: A Distributed Asymmetric Core-Based Micro-Kernel for Big Data Processing

Big Data applications have demanding expectations on computational resources front. Thus, general purpose operating systems are not a good fit. In this paper, we present a new special purpose distributed micro-kernel designed with big data applications’ needs in mind. The new micro-kernel adopts a core-based Asymmetric Multiprocessing (AMP) approach. It optimizes interrupt management and I/O to suit the Map-Reduce model. The proposed micro-kernel design is based on Inter-processor Interrupts over Ethernet (IPIoE) frames and a BareMetal Operating System Markup Language (BOSML). A transparent deployment mechanism is presented to completely shield the developer of the micro-kernel service from the underlying distribution infrastructure and decouple the application implementation from its deployment perspective. Based on the initial prototype and the experiments presented, a considerable gain in performance of average 2.34 folds was achieved using the distributed TeraSort benchmark over Linux/Hadoop.

Energy consumption model in multicore architectures with variable frequency

Models extending Amdahl’s law have been developed to study the behavior of parallel programs energy consumption. In addition, it has been shown that energy consumption of those programs also relies on the layout of the resources on the chip, such as power supply. Other extensions over Amdahl’s law have been conducted to study the behavior of parallel programs speedup for frequency variable processors. Previous models have focused on the use of Turbo Boost in the parallel regions of a program, without considering that Turbo Boost also affects the sequential regions. Hence, we present a model to analyze energy consumption of parallel programs executed on Intel multicore processors with Turbo Boost frequencies to cover this gap. The model is an extension to Amdahl’s law, and it is validated with a double-precision matrix multiplication running on Intel multicore processors that enable Turbo Boost technology.

Investigation of single event effect in 28-nm system-on-chip with multi patterns**Project supported by the National Natural Science Foundation of China (Grant Nos. 11575138, 11835006, 11690040, and 11690043), the Fund from Innovation Center of Radiation Application (Grant No. KFZC2019050321), the Fund from the Science and Technology on Vacuum Technology and Physics Laboratory, Lanzhou Institute of Physics (Grant No. ZWK1804), and the

Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

Appropriate allocation of workloads on performance asymmetric multicore architectures via deep learning algorithms

Asymmetric multicore processors (AMP) have become popular in both high-end and low-end computing systems due to its flexibility and high performance. A performance asymmetric multicore architecture (P-AMP) is the subcategory of AMP, which integrates the different micro-architecture cores in the same chip. Due to the heterogeneity nature of cores and applications, recognizing an optimal hardware configuration in terms of core, voltage-frequency pair for each application is still an NP-hard problem. Optimization of energy-delay product (EDP) is an additional challenging task in such architectures.To address these challenges, we developed a novel core prediction model called lightweight-deep neural network (LW-DNN) for asymmetric multicore processors. The proposed LW-DNN includes three phases, feature selection, feature optimization, and core prediction module. In the first and second phases, workload characteristics are extracted and optimized using the pre-processing algorithm and in the third phase, it predicts the appropriate cores for each workload at runtime to enhance the energy-efficiency and performance.We modeled a deep learning neural network using scikit-learn python library and evaluated in ODROID XU3 ARM big-Little performance asymmetric multicore platform. The embedded benchmarks we considered are MiBench, IoMT, Core-Mark workloads. The proposed LW-DNN prediction module compared with other traditional algorithms in terms of accuracy, execution time, energy consumption, and energy-delay product. The experimental results illustrate that accuracy achieved up to 97% in core prediction, and the average improvement in minimization of energy consumption is 33%, 35% in energy-delay product, 33% minimized in execution time correspondingly.

Parameter Extraction of PSP MOSFET Model in Multi-core Zynq SoC Platform

Abstract Zynq System on Chip (SoC) is widely used architecture to accelerate the computational intensive application with its ARM Processing System (PS) and FPGA fabric - Programmable Logic (PL). In this paper, parameter extraction of PSP MOSFET model is studied as a computational intensive process and its function is accelerated by HW/SW co-design on Zynq SoC using its dual-core Asymmetric Multiprocessing (AMP) architecture. Particle Swarm Optimization (PSO) algorithm is being applied to extract PSP model parameters in order to accurately match the model generated response with measured characteristic. This paper presents the acceleration model for two major processes of parameter extraction: 1) Optimization algorithm (PSO), and 2) Model library (SiMKit) execution. First, the PSO algorithm is implemented as hardware on PL. Second, PSP MOSFET library SiMKit is implemented as a software on PS. Implementation results show 73.06% improvement in PSO execution time compared to ARM-based software implementation. Dual-core AMP configuration results into 28.54% better performance in SiMKit execution time compared to a single-core processor.

A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers

In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58% when the charger operates in the turbo boost mode, and achieves 97% maximum efficiency when the charger operates in buck charge mode.

ON THE CONSTRUCTION OF A SOFTWARE ARCHITECTURE FORNUCLEAR SYSTEMS ON A CRYSTAL

The article discusses how to build software architecture for multi-core systems on a chip (SoC), based on asym-metric and symmetric multiprocessing, the hypervisor. Asymmetric multiprocessing is a port for several operating systems on physi-cally separate processor cores. In symmetric multiprocessing in systems with core isolation, one OS is launched on several cores. OS SMP-system is ported without user intervention with a growing number of cores. Since all cores are managed by a single OS, message transfer between cores can occur at the L1 data cache level, providing faster communication with less jitter. Kernel isola-tion allows you to reserve a kernel for a hard real-time application, protecting it from the influence of other high-performance ker-nels, which for the software architecture allows you to select your operating system without creating low-level software when man-aging multiple operating systems. The hypervisor refers to a low-level software system. It manages several independent operating systems that are at a higher level. Developing multi-core systems-on-chip offerings focused on the embedded market are well suited for asymmetric multiprocessing configurations. This architecture is useful for developers who use the performance of a real-time operating system in combination with a diverse set of Linux kernel functions. The article discusses the software and hardware solu-tions contained in the XAPP1079 environment, which are required to run Linux on a single Zynq-7000 All Programmable system on a chip, and open source applications on the second core. Designing systems based on systems on a chip for high-performance and аreal-time applications requires an optimal solution taking into account the factors: data transfer time; separation of the operating system. A system solution for high-performance and real-time applications using a symmetric multiprocessor processing architecture with kernel isolation provides low latency, jitter and real-time system operation, while maintaining software SoC scalability. Pro-grammable logic integrated circuits containing multi-core subsystems have an efficient architecture with symmetric multiprocessing of data to ensure a compromise between the actual data transfer time and the low latency of their processing. The advantages of using symmetric multiprocessing manifest themselves if the load is distributed among several resources. In this case, the time re-quired to complete the task is reduced. However, the performance gain brought about by a simple multiplication of the number of performers will not necessarily be linear. Some tasks should be performed only sequentially. Multi-core systems are able to process packages much more efficiently than single-core ones -but only if they are managed by optimized software. It is expedient to develop multi-core computing software, including an OS with support for symmetric and asymmetric multiprocessor data processing archi-tectures, an embedded hypervisor, high-speed packet processing modules, and an exhaustive set of tools for the entire cycle of multi-core computing systems. The results of such development will find application in multiprocessor supercomputers and server applica-tions, in terminal devices, access aggregators and basic devices -where the highest throughput is required.

On the maturity of parallel applications for asymmetric multi-core processors

Asymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper performs the first extensive evaluation of how portable are the current HPC applications for such supercomputing systems. Specifically we evaluate several execution models on an ARM big.LITTLE AMC using the PARSEC benchmark suite that includes representative highly parallel applications. We compare schedulers at the user, OS and runtime levels, using both static and dynamic options and multiple configurations, and assess the impact of these options on the well-known problem of balancing the load across AMCs. Our results demonstrate that scheduling is more effective when it takes place in the runtime system level as it improves the baseline by 23%, while the heterogeneous-aware OS scheduling solution improves the baseline by 10%.