Aspect Ratio Dependent Etching Research Articles

Ordered silicon nanocone fabrication by using pseudo-Bosch process and maskless etching

Nanocone arrays are widely employed for applications such as antireflection structures and field emission devices. Silicon nanocones are typically obtained by an etching process, but the profile is hard to attain because anisotropic dry etching generally gives vertical or only slightly tapered sidewall profiles, and isotropic dry plasma etching gives curved sidewalls. In this work, we report the fabrication of cone structures by using masked etching followed by maskless etching techniques. The silicon structure is first etched using fluorine-based plasma under the protection of a hard metal mask, with a tapered or vertical sidewall profile. The mask is then removed, and maskless etching with an optimized nonswitching pseudo-Bosch recipe is applied to achieve the cone structure with a sharp apex. The gas flow ratio of C4F8 and SF6 is significantly increased from 38:22 (which creates a vertical profile) to 56:4, creating a taper angle of approximately 80°. After subsequent maskless etching, the sidewall taper angle is decreased to 74°, and the structure is sharpened to give a pointed apex. The effect of an oxygen cleaning step is also studied. With the introduction of periodic oxygen plasma cleaning steps, both the etch rate and surface smoothness are greatly improved. Lastly, it was found that the aspect ratio-dependent etching effect becomes prominent for dense patterns of cone arrays, with a greatly reduced etch depth at a 600 nm pitch array compared to a 1200 nm pitch array.

Bias-supply timing tailored to the aspect ratio dependence of silicon trench etching in Ar plasma with alternately injected C4F8 and SF6

In semiconductor device fabrication, the feature profiles of a high-aspect-ratio (HAR) Si trench is needed to be controlled considering aspect-ratio-dependent etching (ARDE). This is achieved by a cyclic process in which Ar plasma is sustained while C4F8 and SF6 are alternately injected and a short-period supply of a substrate bias is provided. Presently, the transient behaviors of gaseous and surface reactions are dynamically revealed by measuring the plasma parameters using a surface wave probe and optical emission spectroscopy. When the etched surface is fluorinated during the cycle, an ARDE-free Si-trench feature profile can be fabricated by controlling the bias-supply timing.

Asynchronously Pulsed Plasma for High Aspect Ratio Nanoscale Si Trench Etch Process

The fabrication of high aspect ratio Si trenches has been becoming difficult due to the decrease in critical dimension (CD) to deep nanoscale. Especially, aspect ratio dependent etching (ARDE), which decreases the etch rate as the pattern width gets smaller, makes process uniformity get worse. In this study, the effects of bias pulsing parameters during asynchronous pulsing, which alternatively applies the source power and bias power, as well as the effect of additive gas such as CF4 and C4F8 on the nanoscale Si trench etch characteristics during Cl2/Ar plasma etching were investigated. It was found that the bias pulsing parameters during the asynchronous pulsing, such as bias pulse duty ratio and bias pulse delay time, can affect the etch characteristics such as etch rate, etch selectivity, and ARDE by changing the ion dose and ion energy during the etching. However, the variation of bias pulse parameters during the asynchronous pulsing did not change the etch profile noticeably, and it showed bowed Si trench etch profiles. To improve the etch profile, the addition of fluorocarbon gas such as CF4 and C4F8 was required, and by using C4F8 instead of CF4, more anisotropic Si etch profile without sidewall bowing could be obtained due to the improved sidewall passivation by a fluorocarbon layer even though it degraded etch selectivity and ARDE. Therefore, it is believed that by controlling the bias pulsing parameters with additive gas, nanoscale Si trench etch characteristics can be more easily controlled.

On the origin and evolution of hotspots in multipatterning processes

Understanding the origins and propagation of defects and hotspots in patterning processes used for semiconductor fabrication is of paramount importance in managing yield. In this paper, results from physics-based simulators to model lithography and dry etch processes are presented and compared to experimental results. These models are used to study different types of hotspots and defects observed in a litho-etch-litho-etch (LELE) multipatterning process. At each pass of the LELE flow, patterns are printed into a SiO2 collecting layer using a trilayer film stack comprised of a negative tone photoresist layer, a spin-on-glass layer (SOG), and a spin-on-carbon layer (SOC). After both passes of the LELE process, the patterns in the SiO2 collecting layer will be transferred to a TiN hardmask prior to final etch into an underlying dielectric. The SOG and SiO2 layers are etched using fluorocarbon plasma, while the SOC layer is etched with an H2/N2 plasma generated in a capacitively coupled plasma source. A pinching hotspot is observed during the single litho-etch pass in a region where two features are placed very close and the image contrast is low. However, for some lithography process conditions, this hotspot is rectified by subsequent etch steps and does not always transfer as a defect into the SiO2 layer. The quenching of the hotspot occurs primarily during the etching of the SOC layer due to the aspect ratio-dependent etching (ARDE) effect. A bridging hotspot is also observed at lithography during the single litho-etch pass at high exposure doses. This hotspot, on the other hand, is exacerbated by the etch steps because of the ARDE effect. Hotspots are also identified that originate from overlay errors between photomasks exposed during first and second passes of the LELE process. The etch bias generated during etching of the SOG layer is crucial to ensure that the overlay-related hotspot does not translate to the SiO2 layer. The extent of etch bias in the SOG etch step is critical and can be tuned by adjusting the neutral to ion flux ratio during that etch step. Increasing the flux ratio improves the process window for the overlay defect; however, when the ratio is higher than approximately 20% of the nominal value, a different defect type is formed in the SOG layer due to the inverse ARDE effect that propagates downstream to the SiO2 layer.

Assessing neutral transport mechanisms in aspect ratio dependent etching by means of experiments and multiscale plasma modeling

Since the onset of pattern transfer technologies for chip manufacturing, various strategies have been developed to circumvent or overcome aspect ratio dependent etching (ARDE). These methods have, however, their own limitations in terms of etch non-idealities, throughput or costs. Moreover, they have mainly been optimized for individual in-device features and die-scale patterns, while occasionally ending up with poor patterning of metrology marks, affecting the alignment and overlay in lithography. Obtaining a better understanding of the underlying mechanisms of ARDE and how to mitigate them therefore remains a relevant challenge to date, for both marks and advanced nodes. In this work, we accordingly assessed the neutral transport mechanisms in ARDE by means of experiments and multiscale modeling for SiO2 etching with CHF3/Ar and CF4/Ar plasmas. The experiments revealed a local maximum in the etch rate for an aspect ratio around unity, i.e. the simultaneous occurrence of regular and inverse reactive ion etching lag for a given etch condition. We were able to reproduce this ARDE trend in the simulations without taking into account charging effects and the polymer layer thickness, suggesting shadowing and diffuse reflection of neutrals as the primary underlying mechanisms. Subsequently, we explored four methods with the simulations to regulate ARDE, by varying the incident plasma species fluxes, the amount of polymer deposition, the ion energy and angular distribution and the initial hardmask sidewall angle, for which the latter was found to be promising in particular. Although our study focusses on feature dimensions characteristic to metrology marks and back-end-of-the-line integration, the obtained insights have a broader relevance, e.g. to the patterning of advanced nodes. Additionally, this work supports the insight that physisorption may be more important in plasma etching at room temperature than originally thought, in line with other recent studies, a topic on which we recommend further research.

Etched characteristics of nanoscale TiO2 using C4F8-based and BCl3-based gases

TiO2 is a material used in various fields such as electronics, optics, environment, etc. For the application to electronic and optical devices, TiO2 needs to be patterned using reactive ion etching using halogen-based gases. In this study, a TiO2 masked with ACL pillar pattern was etched using two types of gases namely C4F8-based (C4F8/SF6/Ar) and BCl3-based (BCl3/CF4/Ar), and the effect of etch gas and asynchronous pulsing (separated source power ON time and bias power ON time in a pulse period) on the etch properties such as the etch rates, etch selectivity, and aspect ratio dependent etching (ARDE) were investigated. The use of asynchronous pulsing with decreased bias pulsing ratio (high source power ON time and low bias ON time in a pulse period) improved the etch selectivity and ARDE possibly due to the lower sputter etching time after the removal of reacted species on the TiO2 surface and due to the more similar etch environment for different aspect ratio TiO2 features, respectively. The use of BCl3-based plasma showed higher etch selectivity over ACL compared to C4F8-based plasma, however, it showed the lower etch rate and more severe ARDE due to the stickiness of Cl compared to F to the sidewall during the etching of high aspect ratio TiO2.

Effect of various pulse plasma techniques on TiO2 etching for metalens formation

TiO2 meta materials composed of high aspect ratio pillars with different widths can be used for a planar metalens with a thickness that are less than a sheet of paper and with no chromatic aberrations. In this study, TiO2 pillars with different sizes masked by ACL were etched with an inductively coupled plasma (ICP) etcher and a gas mixture of C4F8/SF6/Ar using various plasma techniques such as continuous wave (CW), bias pulsing, synchronous pulsing, and asynchronous pulsing and their TiO2 etch characteristics and plasma characteristics were compared. The results showed that the etch rates were decreased in the sequence of CW, bias pulse, synchronous pulse, and asynchronous pulse conditions. However, the etch selectivities over ACL and SiO2 and the aspect ratio dependent etching (ARDE) effect were improved in that sequence. The decrease in etch rates in that sequence was related to no power input during the processing such as no ICP source power and/or no bias power at those pulse conditions. And, the increase of etch selectivities was related to the increased CFx/F and CFx(x = 2,3)/CF in the plasmas due to less dissociation and/or more recombination of fluorocarbon gas during the pulse conditions. The improvement of the aspect ratio dependent etching (ARDE) effect was caused by the decreased compositional differences between wide TiO2 pattern area and narrow TiO2 pattern area. Especially, the ARDE effect was the lowest for the asynchronous pulse condition due to the cyclic etch characteristics composed of the reactant chemisorption step by supplying ICP power only and the etch step by supplying bias power only similar to atomic layer etching (ALE).

Evolution of lithography-to-etch bias in multi-patterning processes

Quantitatively accurate, physics-based, computational modeling of etching and lithography processes is essential for modern semiconductor manufacturing. This paper presents lithography and etch models for a trilayer process in a back end of the line manufacturing vehicle. These models are calibrated and verified against top-down scanning electron microscope (SEM) and cross-sectional SEM measurements. Calibration errors are within 2 nm, while the maximum verification error is less than 3 nm. A fluorocarbon plasma etch of the spin-on-glass (SOG) layer accounts for most of the etch bias present in the process. The tapered profile in the SOG etch step is generated due to the polymerization process by fluorocarbon radicals generated in the plasma. The model predicts a strong correlation between the etch bias in the SOG etch step and the neutral-to-ion flux ratio in the plasma. The second etch step of the flow, which etches the spin-on-carbon (SOC) layer using an H2/N2 plasma, results in a negative etch bias (increase in CDs) for all measured features. The ratio of hydrogen to nitrogen radical fluxes effectively controls the etch bias in this step, with the model predicting an increase in the etch bias from negative to positive values as the H-to-N ratio decreases. The model also indicates an aspect ratio dependent etch rate in the SOG and SOC etch steps, as seen in the etch front evolution in a three-dimensional test feature. The third and final step of the process, SiO2-etch, generates an insignificant etch bias in all the test structures. Finally, the accuracy of the etch simulations is shown to be dependent on the accuracy of the incoming photoresist shapes. Models that consider only the top-down SEM measurement as input and do not account for an accurate photoresist profile, suffered significant errors in the post-etch CD predictions.

The Impact of Manufacturing Imperfections on the Performance of Metalenses and a Manufacturing-Tolerant Design Method.

Metalenses play an important role in optoelectronic integrated devices, given their advantages in miniaturization and integration. Due to its high aspect ratio subwavelength structure, fabricating metalenses requires a high-level dry etching technology. Consequently, structure deformation of the metalens will exist if the etching process of the material is not mature enough, which will impair the metalens’ performance. In this paper, a polarization-independent InP dielectric metalens is designed to focus the incident light from air into the substrate, which is used for monolithically integrating with the InGaAs/InP photodetector in the future. Subsequently, with the simulation method, we investigated the impact of the structure deformation on the metalens’ performance, which was found in our InP dry etching process development. We have found that the sidewall slope and aspect ratio-dependent etching effect greatly impaired the focusing efficiency because of the phase modulation deviation. To solve this problem, we proposed a manufacturing-tolerant design method, which effectively improved the performance of the device with structural deformation. Our work is instructive for developing metalenses and can accelerate their integration application.

Simultaneous Micro- and Nanoscale Silicon Fabrication by Metal-Assisted Chemical Etch

Abstract Simultaneous micro- and nanoscale etching of silicon on a wafer-scale is nowadays performed using plasma etching techniques. These plasma techniques, however, suffer from low throughput due to aspect-ratio dependent etch (ARDE) rate, etch lag from changes in feature size, loading effects from increased etch area, and undesirable surface characteristics such as sidewall taper and scalloping, which are particularly problematic at the nanoscale and can affect the etch uniformity. Additionally, the hardware required for plasma etching can be very expensive. A potential alternative, which addresses the above issues with plasma etching is metal assisted chemical etch (MacEtch). To date, however, an integrated micro- and nanoscale MacEtch process, which has uniform and clean (i.e., without nanowire-like defects in microscale areas) etch front has not been presented in the literature. In this work, we present for the first time a feasible process flow for simultaneous micro-and nanoscale silicon etching without nanowire-like defects, which we call integrated micro- and nanoscale MacEtch (IMN-MacEtch). Successful etching of silicon features ranging from 100 nm to 100 μm was achieved with etch rates of about 1.8 μm/min in a single step to achieve features with an aspect ratio (AR) ∼18:1. We thus conclude that the process represents a feasible alternative to current dry etch methods for patterning feature sizes spanning three orders of magnitude.

Effect of different pulse modes during Cl2/Ar inductively coupled plasma etching on the characteristics of nanoscale silicon trench formation

The etch characteristics of silicon trenches masked with various SiO2/Si3N4pattern distances were investigated using synchronously and asynchronously pulse modes in addition to the continuous wave (CW) mode for Ar/Cl2inductively coupled plasmas. By using synchronously and asynchronously pulse modes instead of CW mode, the selectivity between Si and the mask layer was increased by 2 and 10 times, respectively. Also,the etch rate differences between wide and narrow pattern distance patterns (aspect ratio dependent etching, ARDE) was decreased from 35% to 21 and to 8%,respectively. The increased etch selectivity andreduction of ARDE for the synchronously pulsed mode were related to the increased conduction of Cl radicals/byproductsthrough the high aspect ratio trench, therefore, increased chemisorption/byproduct removal on the silicon trench surface during the pulse-off period. For the asynchronously pulsed mode, the further improved etch selectivity and reduced ARDE were believed to be related to the time separated etch cycle composed of Cl chemical adsorption on the silicon trench surface and the removal of the chemisorbed species by ion bombardment. It is believed that, the asynchronously pulsed plasma etching method can be applicable to various next generation deep nanoscale device fabrication requiring high etch selectivity and low ARDE.

Etch-free additive lithographic fabrication methods for reflective and transmissive micro-optics.

With the widespread application of micro-optics in a large range of areas, versatile high quality fabrication methods for diffractive optical elements (DOEs) have always been desired by both the research community and by industry. Traditionally, multi-level DOEs are fabricated by a repetitive combination of photolithography and reactive-ion etching (RIE). The optical phase accuracy and micro-surface quality are severely affected by various etching artifacts, e.g., RIE lag, aspect ratio dependent etching rates, and etching artifacts in the RIE steps. Here we propose an alternative way to fabricate DOEs by additively growing multi-level microstructures onto the substrate. Depth accuracy, surface roughness, uniformity and smoothness are easily controlled to high accuracy by a combination of deposition and lift-off, rather than etching. Uniform depths can be realized for both micrometer and millimeter scale features that are simultaneously present in the designs. The grown media can either be used directly as a reflective DOE, or as a master stamp for nanoimprinting refractive designs. We demonstrate the effectiveness of the fabrication methods with representative reflective and transmissive DOEs for imaging and display applications.

Etch characteristics of Si and TiO2 nanostructures using pulse biased inductively coupled plasmas

The etch characteristics of Si and TiO2 nanostructures for optical devices were investigated using pulse biased inductively coupled plasmas (ICP) with SF6/C4F8/Ar and BCl3/Ar, respectively, and the results were compared with those etched using continuous wave (CW) biased ICP. By using pulse biasing compared to CW biasing in the etching of the line/pillar nanostructures with various aspect ratios, there was a reduction of the aspect ratio dependent etching (ARDE) and therefore, uniform etch depths for nanostructures with different pattern widths, as well as the improvement of the etch profiles without any notching, were obtained not only for silicon nanostructures but also for TiO2 nanostructures. The investigation has determined that the improvement of etch profiles and reduced ARDE effect when using pulse biasing are related to the decreased surface charging caused by neutralization of the surface and the improved radical adsorption (or etch byproduct removal) on the etched surfaces during the pulse-off period for pulse biasing compared to CW biasing.

Plasma etching of high aspect ratio features in SiO2 using Ar/C4F8/O2 mixtures: A computational investigation

Plasma etching of high aspect ratio (HAR) features, typically vias, is a critical step in the fabrication of high capacity memory. With aspect ratios (ARs) exceeding 50 (and approaching 100), maintaining critical dimensions (CDs) while eliminating or diminishing twisting, contact-edge-roughening, and aspect ratio dependent etching (ARDE) becomes challenging. Integrated reactor and feature scale modeling was used to investigate the etching of HAR features in SiO2 with ARs up to 80 using tri-frequency capacitively coupled plasmas sustained in Ar/C4F8/O2 mixtures. In these systems, the fluxes of neutral radicals to the wafer exceed the fluxes of ions by 1–2 orders of magnitude due to lower threshold energies for dissociation compared with ionization. At low ARs (<5), these abundant fluxes of CFx and CxFy radicals to the etch front passivate the oxide to form a complex which is then removed by energetic species (ions and hot neutrals) through chemically enhanced reactive etching, resulting in the formation of gas phase SiFx, COx, and COF. As the etching proceeds into higher ARs, the fractional contribution of physical sputtering to oxide removal increases as the fluxes of energetic species to the etch front surpass those of the conduction constrained CFx and CxFy radicals. The instantaneous etch rate of oxide decreases with increasing aspect ratio (ARDE effect) due to decreased fluxes of energetic species and decreased power delivered by these species to the etch front. As the etch rate of photoresist (PR) is independent of AR, maintaining CDs by avoiding undercut and bowing requires high SiO2-over-PR selectivity, which in turn requires a minimum thickness of the PR at the end of etching. Positive ions with narrow angular distributions typically deposit charge on the bottom of low AR features, producing a maximum in positive electric potential on the bottom of the feature. For high AR features, grazing incidence collisions of ions on sidewalls depositing charge produce electric potentials with maxima on the sidewalls (as opposed to the bottom) of the feature.

Hybrid lithography based fabrication of 3D patterns by deep reactive ion etching

Electron-beam lithography (EBL) possesses tremendous capabilities in terms of patterning ultra-small features, with very low line edge roughness and high overlay accuracy. In order to reduce write times and processing steps, hybrid lithography is an interesting alternative. Here, an approach combining EBL and ultraviolet lithography (UVL) was pursued in order to pattern multi-level 3D-structures by inductively coupled plasma deep reactive ion etching (ICP-DRIE). The substrate etched hereby consisted of a silicon nitride thin film and the underlying silicon. The correlation of UVL under- and overexposures with the resist layer height and sidewall taper after development, in combination with the optimization of the ICP-DRIE selectivity in dependence of the biasing conditions and the aspect ratio dependent etch lag for small features, allowed for the accurate prediction and therefore programming of the desired structures. Further, the selectivity was tailored by introducing an oxygen pulse after the breakthrough step. This facilitated the simultaneous etching of structures with an in-plane resolution of down to 250 nm (aspect ratio 1:22) and trench depths ranging from 200 nm to 25 μm.

Physics-Prior Bayesian Neural Networks in Semiconductor Processing

With the fast scaling-down and evolution of integrated circuit (IC) manufacturing technology, the fabrication process becomes highly complex, and the experimental cost of the processes is significantly elevated. Therefore, in many cases, it is very costly to obtain a sufficient amount of experimental data. To develop an efficient method to predict the results of semiconductor experiments with a small amount of known data, we use a novel method based on Bayesian framework with the prior distribution constructed by technology computer-aided-design (TCAD) physical models. This method combines the advantages of statistical models and physical models in the aspect that TCAD can provide visionary guidance on an experiment when a limited amount of experimental data is available, and a machine learning model can account for subtle anomalous effects. Specifically, we use aspect ratio dependent etching (ARDE) phenomenon as an example and use variational inference with Kullback-Leibler divergence minimization to achieve the approximation to the posterior distribution. The relation between etching process input parameters and etching depth is learned using the Bayesian neural network with TCAD priors. Using this method with 35 neurons per hidden layer, mean square error (MSE) in the test set is reduced from 0.2896 to 0.0175, 0.058 to 0.0183, 0.0563 to 0.0188, 0.058 to 0.019 for partition=10, 20, 30, 40, respectively, reference to the baseline BNN where a regular normal distribution prior with zero mean and unity standard deviation N(0,1) is used.

(Invited) Atomic Layer Processing from an Etching Perspective

Atomic Layer Etching (ALE) transitioned to manufacturing because of unique performance benefits which come from self-saturation of the steps and the use of very low ion energies or just thermal means to remove material. The former property gives uniformity across all lengths scales on the wafer. Reduced aspect ratio dependent etching (ARDE) and surface smoothness are very attractive benefits. Low level removal energies deliver selectivity which is a key requirement for etching with atomic scale fidelity. In this talk, a conceptual framework for directional and isotropic ALE will be compared to other etching technologies for semiconductor devices. Recent experimental and theoretical results as well as applications examples will be presented to illustrate the concepts.

Intelligent Manufacturing: TCAD-Assisted Adaptive Weighting Neural Networks

Using machine intelligence on device and process performance prediction is an emerging methodology in the IC industry. While semiconductor technology computer-aided design (TCAD) has been researched and developed for over 30 years, it should contribute to or be used in conjunction with machine learning algorithms in solution finding procedure. Here, we propose an adaptive weighting neural network (AWNN) model that combines the advantages of statistical the machine learning model and the physical TCAD model. Using aspect ratio dependent etching as an example, our proposed AWNN outperforms conventional artificial neural network in terms of mean square errors in the test set where 5-10 times reduction is observed. The effectiveness of the TCAD AWNN model can be especially effective in the case of sampling over a vast sample space since the under-sampling problem can be compensated by the TCAD model. The large and nearly unbounded sample space is very common in IC technology, where cascaded and repeated process steps exist (~150 process steps and ~20 masks for 90-nm CMOS process).

Time multiplexed deep reactive ion etching of germanium and silicon-A comparison of mechanisms and application to x-ray optics.

Although the mechanisms of deep reactive ion etching (DRIE) of silicon have been reported extensively, very little by comparison has been discussed concerning DRIE of germanium. By directly comparing silicon and germanium etching in a time multiplexed DRIE process, the authors extract significant differences in etch mechanisms from a design of experiment and discuss how these differences are relevant to the design and fabrication of silicon and germanium collimating channel array x-ray optics. The differences are illuminated by characteristics such as reactive ion etching (RIE)-lag, aspect ratio dependent etching, and sidewall passivation. Specifically, the authors demonstrate the more severe nature of RIE-lag in germanium, especially at aspect ratios exceeding 13:1. In addition, the differences in the profile evolution between silicon and germanium are shown to be a result of differences in sidewall passivation. There is also a correlation between the different sidewall passivation and the inherent lack of scalloping in the case of germanium DRIE.

Atomic layer etching of 3D structures in silicon: Self-limiting and nonideal reactions

Current (and future) microelectronics fabrication requirements place unprecedented demands on the fidelity of plasma etching. As device features shrink to atomic dimensions, the plasma etching processes used to define these devices must resolve these scales. By separating etching processes into cycles of multiple, self-limited steps, different physics processes which are closely coupled in traditional plasma etching can be largely decoupled and separately optimized. This technique, atomic layer etching (ALE), can ideally remove uniform layers of material with consistent thickness in each cycle. ALE holds the promise of improving uniformity, reducing damage, increasing selectivity, and minimizing aspect ratio dependent etching (ARDE) rates. The practical implementation of ALE depends on how close to ideal the system can be operated and the tolerance to nonideal conditions. In this paper, results are discussed from a computational investigation of the consequences of nonidealities in the ALE of silicon using Ar/Cl2 plasmas for both two dimensional trenches and three dimensional features. The authors found that ideal ALE requires self-limited processes during all steps of the ALE cycle. Steps that include continuous (non-self-limited) etching reactions reduce the ability of ALE to decouple process parameters. In addition to an etch depth that depends on pulse length per cycle, non-self-limited processes can reintroduce ARDE and produce surface roughening. By controlling subcycle pulse times, these deleterious effects can be minimized, and many of the benefits of ALE can be restored. Even nonideal ALE processes, when properly optimized, still provide benefits over continuous etching with similar chemistries and ion energy distributions. Using fluxes generated by a conventional inductively coupled plasma reactor, an example ALE process is able to clear the corners in a three-dimensional fin based field effect transistor case study with significantly less over-etch than the continuous process.