Array Of Functional Units Research Articles

Stimulus dependent diversity and stereotypy in the output of an olfactory functional unit

Olfactory inputs are organized in an array of functional units (glomeruli), each relaying information from sensory neurons expressing a given odorant receptor to a small population of output neurons, mitral/tufted (MT) cells. MT cells respond heterogeneously to odorants, and how the responses encode stimulus features is unknown. We recorded in awake mice responses from “sister” MT cells that receive input from a functionally characterized, genetically identified glomerulus, corresponding to a specific receptor (M72). Despite receiving similar inputs, sister MT cells exhibit temporally diverse, concentration-dependent, excitatory and inhibitory responses to most M72 ligands. In contrast, the strongest known ligand for M72 elicits temporally stereotyped, early excitatory responses in sister MT cells, consistent across a range of concentrations. Our data suggest that information about ligand affinity is encoded in the collective stereotypy or diversity of activity among sister MT cells within a glomerular functional unit in a concentration-tolerant manner.

Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor

In the billion transistor era only a few architectural approaches propose new paths to improve the execution of conventional sequential instruction streams. Many legacy applications could profit from processors that are able to speed-up the execution of sequential applications beyond the performance of current superscalar processors. The Grid arithmetic logic unit (ALU) Processor (GAP) accelerates conventional sequential instruction streams without the need for recompilation. The GAP comprises a processor front-end similar to that of a superscalar processor extended by a configuration unit and a two-dimensional array of functional units that forms the execution unit. Instruction sequences are mapped dynamically into the array by the configuration unit so that they form the dataflow graph of the sequence. This study shows a performance evaluation of the GAP architecture with different array dimensions as well as its performance using a simplified interconnection network. GAP outperforms an out-of-order superscalar processor by a maximum of factor 2 with a complete crossbar interconnect between two array rows. Reducing the interconnection network to the minimum shows a maximum performance drawback of 10% for only a particular configuration and a single benchmark. In general, the slowdown is less than 2% for the minimum interconnect (two buses) and about 0.02% if three interconnection buses are used.

MT-ADRES: multi-threading on coarse-grained reconfigurable architecture

The coarse-grained reconfigurable architecture ADRES (architecture for dynamically reconfigurable embedded systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl's law, this article proposes to extend ADRES to MT-ADRES (multi-threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.