ARM Processor Research Articles

A Proof-of-Concept Open-Source Platform for Neural Signal Modulation and Its Applications in IoT and Cyber-Physical Systems

This paper presents the design, implementation, and characterization of a digital IoT platform capable of generating brain rhythm frequencies using synchronous digital logic. Designed with the Google SkyWater 130 nm open-source process design kit (PDK), this platform emulates Alpha, Beta, and Gamma rhythms. As a proof of concept and the first of its kind, this device showcases its potential applications in both industrial and academic settings. The platform was integrated with an IoT device to optimize and accelerate research and development efforts in embedded systems. Its cost-effective and efficient performance opens opportunities for real-time neural signal processing and integrated healthcare. The presented digital platform serves as a valuable educational tool, enabling researchers to engage in hands-on learning and experimentation with IoT technologies and system-level hardware–software integration at the device level. By utilizing open-source tools, this research demonstrates a cost-effective approach, fostering innovation and bridging the gap between theoretical knowledge and practical application. Furthermore, the proposed system-level design can be interfaced with various serial devices, Wi-Fi modules, ARM processors, and mobile applications, illustrating its versatility and potential for future integration into broader IoT ecosystems. This approach underscores the value of open-source solutions in driving technological advancements and addressing skills shortages.

Performance Analysis of Spin Orbit Torque Magneto-Resistive RAM Caches in 4-core ARM Systems

Spin Orbit Torque Magnetic Random Access Memory (SOT–)MRAM is gaining interest as it eradicates several limitations posed by its predecessor Spin Transfer Torque (STT-)MRAM, yet inherits all its advantages. This work explores in detail, the suitability of SOT–MRAM implemented caches in different levels of memory hierarchy in comparison to conventional SRAM technology, over several performance parameters like area, energy consumption and execution time for an embedded benchmark suite. Our circuit-level analysis shows that SOT–MRAM outperforms SRAM for caches ([Formula: see text] KB), and only lags in area and read-access energy for smaller caches. A typical 512 KB SOT–MRAM cache improves area by 1%, read/write latency by 33/38%, and leakage by over 99% than that of SRAM memory technology. The architecture-level analysis confirms that on average SOT–MRAM is energy efficient by 74% in L1, 97.2% in L2 and 89.3% in both (i.e., L1 + L2) implementations against SRAM, for a 22[Formula: see text]nm technology node. We also estimate that SOT–MRAM only solution offers [Formula: see text]% energy savings and [Formula: see text]% better EDP than Hybrid (L1-SRAM and L2-SOT) memory hierarchy for multi-core ARM processors.

HAETAE on ARMv8

In this work, we present the highly optimized implementation of the HAETAE algorithm, submitted to the second round of the Korean Post-Quantum Cryptography (KpqC) competition and to the first round of NIST’s additional post-quantum standardization for digital signatures on 64-bit ARMv8 embedded processors. To the best of our knowledge, this is the first optimized implementation of the HAETAE algorithm on 64-bit ARMv8 embedded processors. We apply various optimization techniques to enhance the multiplication operations in the HAETAE algorithm. We utilize parallel operation techniques involving vector registers and NEON (Advanced SIMD technology used in ARM processors) instructions of ARMv8 embedded processors. In particular, we achieved the best performance of the HAETAE algorithm on ARMv8 embedded processors by applying all the state-of-the-art NTT (Number Theoretic Transform) implementation techniques. Performance improvements of up to 3.07×, 3.63×, and 9.15× were confirmed for NTT, Inverse-NTT, and pointwise Montgomery operations (Montgomery multiplication used in modular arithmetic), respectively, by applying the state-of-the-art implementation techniques, including the proposed techniques. As a result, we achieved a maximum performance improvement of up to 1.16× for the key generation algorithm, up to 1.14× for the signature algorithm, and up to 1.25× for the verification algorithm.

Real-time fault-tolerant guidance for launch vehicle ascending flight under thrust drop failure

This paper presents a real-time fault-tolerant guidance method, which solves the autonomous rescue problem in the event of thrust drop failure during the final stage flight of launch vehicles. The core of the method is the online and optimal reconstruction of both the degraded target orbit and the subsequent flight trajectory. Aiming at achieving satisfied onboard computing performance and making the best use of the launcher’s residual energy, a unique relaxation-penalization model transformation method for the nonlinear orbit injection conditions is proposed, and a successive convexification algorithm is developed to solve the problem. Furthermore, both the two classic thrust drop failure situations, that is the mass flow rate drop and the specific impulse drop problems, can be resolved by the proposed algorithm. The average run-time of this orbit-trajectory joint optimization algorithm is below 150ms in an embedded ARM processor @1.5 GHz, which is adequate for onboard use. Using the above algorithm as a central infrastructure, a receding-horizon-strategy-based fault-tolerant guidance method is proposed. By performing the optimization repeatedly at a high frequency, the effects of parameter deviations and external disturbances can be absorbed for the most part, for example, the guidance algorithm is verified to be capable of tolerating at least ±5% thrust deviations. Comprehensive numerical and hardware-in-the-loop simulations are performed to demonstrate the computational performance, accuracy, and reliability of the proposed algorithms.

Performance Evaluation of Lightweight Stream Ciphers for Real-Time Video Feed Encryption on ARM Processor

Performance Evaluation of Lightweight Stream Ciphers for Real-Time Video Feed Encryption on ARM Processor

Wearable Processors Architecture: A Comprehensive Analysis of 64-bit ARM Processors

Wearable Processors Architecture: A Comprehensive Analysis of 64-bit ARM Processors

Flame Fighter: GPS-Enabled Robot with GSM Communication for Fire Extinguishing

One of the biggest issues our society is currently dealing with is fire accidents. To reduce the likelihood of fire accidents, efficient fire detection and extinguishment procedures should be followed. Fire rescue personnel are currently providing services to put out fires. But occasionally, it might result in firefighters losing their lives. This study suggests utilizing an Arm processor to create a smart, miniature firefighting robot. Without assistance from a human, the suggested robot will autonomously detect and put out fires. An GSM and GPS models can be used to manually control the robot and put out fires. Additionally, the GSM uses alert messages to notify the user of the fire outbreak. Therefore, our method may be utilized to efficiently identify and put out fires in instances when they are starting

Parallel GEMM-based convolutions for deep learning on multicore ARM and RISC-V architectures

We present high performance, multi-threaded implementations of three GEMM-based convolution algorithms for multicore processors with ARM and RISC-V architectures. The codes are integrated into CONVLIB, a library that has the following unique features: (1) scripts to automatically generate a key component of GEMM, known as the micro-kernel, which is typically written in assembly language; (2) a modified analytical model to automatically tune the algorithms to the underlying cache architecture; (3) the ability to select four hyper-parameters: micro-kernel, cache parameters, parallel loop, and GEMM algorithm dynamically between calls to the library, without recompiling it; and (4) a driver to identify the best hyper-parameters. In addition, we provide a detailed performance evaluation of the convolution algorithms, on five ARM and RISC-V processors, and we publicly release the codes.

Performance Comparison of CFD Microbenchmarks on Diverse HPC Architectures

OpenFOAM is a CFD software widely used in both industry and academia. The exaFOAM project aims at enhancing the HPC scalability of OpenFOAM, while identifying its current bottlenecks and proposing ways to overcome them. For the assessment of the software components and the code profiling during the code development, lightweight but significant benchmarks should be used. The answer was to develop microbenchmarks, with a small memory footprint and short runtime. The name microbenchmark does not mean that they have been prepared to be the smallest possible test cases, as they have been developed to fit in a compute node, which usually has dozens of compute cores. The microbenchmarks cover a broad band of applications: incompressible and compressible flow, combustion, viscoelastic flow and adjoint optimization. All benchmarks are part of the OpenFOAM HPC Technical Committee repository and are fully accessible. The performance using HPC systems with Intel and AMD processors (x86_64 architecture) and Arm processors (aarch64 architecture) have been benchmarked. For the workloads in this study, the mean performance with the AMD CPU is 62% higher than with Arm and 42% higher than with Intel. The AMD processor seems particularly suited resulting in an overall shorter time-to-solution.

Chip-Based Electronic System for Quantum Key Distribution.

Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems.

Active and passive virtual machine introspection on AMD and ARM processors

Active and passive virtual machine introspection mechanisms are pivotal for monitoring virtual machines on top of a hypervisor. They enable external tools to monitor and inspect the state from the outside. Active virtual machine introspection mechanisms intercept the execution at predetermined locations of interest synchronous to the execution of the system. Such mechanisms, in particular, require support from the processor vendor by facilitating interpositioning. This support is missing on AMD x86 processors, leading to inferior introspection solutions. We outline implicit assumptions about active introspection mechanisms in previous work, offer constructions for solution strategies on AMD systems, and discuss stealthiness and correctness. We show empirically that such retrofitted software solutions exhibit performance metrics in the same order of magnitude as native hardware solutions. Moreover, we highlight that the open problems for virtual machine introspection on ARM systems and those encountered on AMD x86 are related. Hence, we present an introspection architecture based on KVMi that addresses these open problems. Finally, we demonstrate comparable and, in many cases, superior performance to state-of-the-art solutions on Intel x86.

A Versatile Board for Event-Driven Data Acquisition.

Event-driven data acquisition is used to capture information from fast transient phenomena typically requiring a high sampling speed. This is an important requirement in the ITER Neutral Beam Test Facility for the development of one of the heating systems of the ITER nuclear fusion experiment. The Red Pitaya board has been chosen for this project because of its versatility and low cost. Versatility is provided by the hosted Zynq System on Chip (SoC), which allows full configuration of the module architecture and the OpenSource architecture of Red Pitaya. Price is an important factor, because the boards are installed in a hostile environment where devices can be damaged by EMI and radiation. A flexible solution for event-driven data acquisition has been developed in the Zynq SoC and interfaced to the Linux-based embedded ARM processor. It has been successfully adopted in a variety of data acquisition applications in the test facility.

Armed with Faster Crypto: Optimizing Elliptic Curve Cryptography for ARM Processors

Elliptic curve cryptography is a widely deployed technology for securing digital communication. It is the basis of many cryptographic primitives such as key agreement protocols, digital signatures, and zero-knowledge proofs. Fast elliptic curve cryptography relies on heavily optimised modular arithmetic operations, which are often tailored to specific micro-architectures. In this article, we study and evaluate optimisations of the popular elliptic curve Curve25519 for ARM processors. We specifically target the ARM NEON single instruction, multiple data (SIMD) architecture, which is a popular architecture for modern smartphones. We introduce a novel representation for 128-bit NEON SIMD vectors, optimised for SIMD parallelisation, to accelerate elliptic curve operations significantly. Leveraging this representation, we implement an extended twisted Edwards curve Curve25519 back-end within the popular Rust library “curve25519-dalek”. We extensively evaluate our implementation across multiple ARM devices using both cryptographic benchmarks and the benchmark suite available for the Signal protocol. Our findings demonstrate a substantial back-end speed-up of at least 20% for ARM NEON, along with a noteworthy speed improvement of at least 15% for benchmarked Signal functions.

Design Strategy and Implementation of Control Parameters for BLDC Motor Application in an Electric Vehicle

The brushless dc motor (BLDC) motor is an electric motor that is widely utilized in numerous applications, especially in automotive systems. It is significant to maximize the force of the electric vehicle; however, due to the rapid growth of electric vehicles, motors and power electronics are determined with huge concern. Meanwhile, the Proportional Integral Derivative (PID) cannot balance the load in a stable condition, and this variation generates a change in load and track conditions. In mobile robot the BLDC motor diminished the current and it increased the torque voltage and current by 48V and 50A, respectively. So to overcome these issues, the control algorithm is implemented in this paper to regulate the speed of the motor in 1KW BLDC in an Electric Vehicle (EV). A 1500rpm BLDC motor is designed by Dymola software which is evaluated with MATLAB. The BLDC increases the torque speed characteristics of the motor based on the pole configuration of an electric vehicle. Evaluation of the method is determined with a set of STM 31 ARM processors and a 750 watt driver. The experimentation is simulated using Arduino IDE software and the results revealed that it is applicable for STM 32 or teensy 3.2 development board or Arduino Mega development board.

Accelerating science: The usage of commercial clouds in ATLAS Distributed Computing

The ATLAS experiment at CERN is one of the largest scientific machines built to date and will have ever growing computing needs as the Large Hadron Collider collects an increasingly larger volume of data over the next 20 years. ATLAS is conducting R&D projects on Amazon Web Services and Google Cloud as complementary resources for distributed computing, focusing on some of the key features of commercial clouds: lightweight operation, elasticity and availability of multiple chip architectures. The proof of concept phases have concluded with the cloud-native, vendoragnostic integration with the experiment’s data and workload management frameworks. Google Cloud has been used to evaluate elastic batch computing, ramping up ephemeral clusters of up to O(100k) cores to process tasks requiring quick turnaround. Amazon Web Services has been exploited for the successful physics validation of the Athena simulation software on ARM processors. We have also set up an interactive facility for physics analysis allowing endusers to spin up private, on-demand clusters for parallel computing with up to 4 000 cores, or run GPU enabled notebooks and jobs for machine learning applications. The success of the proof of concept phases has led to the extension of the Google Cloud project, where ATLAS will study the total cost of ownership of a production cloud site during 15 months with 10k cores on average, fully integrated with distributed grid computing resources and continue the R&D projects.

PUF-Kyber: Design of a PUF-Based Kyber Architecture Benchmarked on Diverse ARM Processors

PUF-Kyber: Design of a PUF-Based Kyber Architecture Benchmarked on Diverse ARM Processors

Adaptive Control of a Boost DC/DC Converter based on Artificial Intelligence

The paper presents a solution to model and control the operation of DC/DC converters, in normal regime based on Artificial Intelligence. A solution is developed for simulating and controlling the performance of DC/DC converters, encompassing both normal and fault scenarios. The suggested model for the converter employs a transfer function mathematical model configuration with adaptable coefficients. To accommodate variable duty cycles, fully connected neural networks are utilized to determine the appropriate coefficients for the model. Additionally, a control framework capable of identifying faults and mitigating their impact is presented. This framework includes a compensator designed to prevent unstable conditions as the converter parameters deviate from their nominal values, serving as an effective fault tolerance mechanism. The proposed methodology is aimed at devising algorithms suitable for real-time execution on 32-bit ARM processors.

Impact characterization on thin structures using machine learning approaches

Machine learning algorithms are trained and compared to identify and to characterise the impact on typical aerospace panels of different geometry. Experimental activities are conducted to build a proper impacts’ dataset. Polynomial regression algorithm and artificial neural network are applied and optimised to panels without stringer to test their capability to identify the impacts. Subsequently, the algorithms are applied to panels reinforced with stringers that represent a significant increase of complexity in terms of dynamic features of the system to test: the focus is not only on the impact position’s detection but also on the event’s severity. After the identification of the best algorithm, the corresponding machine learning model is deployed on an ARM processor mini-computer, implementing an impact detection system, able to be installed on board an aerial vehicle, making it a smart aircraft equipped with an artificial intelligence decision-making system.

SIMD implementation of deep CNNs for myopia detection on a single-board computer system

Deep learning algorithms, especially Convolution Neural Networks (CNN), have been rapidly developed due to their flexibility and scalability to be adopted in several fields for modeling real-world applications like object detection, image classification, etc. However, their high accuracy incurs intensive computations. Therefore, it is crucial to carefully choose a suitable computer platform and implementation methodology for CNN network architectures while achieving increased efficiency. Parallel architectures are prevalent in CNN implementation. Herein, we present a new Single Instruction Multi Data (SIMD) parallel implementation of the proposed CNN to speed up the execution process and make it suitable to deploy on low-cost, low-power consumption platforms. The proposed implementation produces an improved model of deep CNN executable on a cost-efficient platform and portability to work autonomously with multi-core processing units while maintaining working accuracy. Raspberry Pi 3 B is a low-power target device for implementing our model. The proposed approach is characterized by high diagnostic accuracy of up to 96.35 % while incurring power consumption of 3.65 Watts, achieving power reduction between 19.17 % and 68.45 % compared to the prior work. Meanwhile, it has a fine inference time for the selected platform. The outstanding results of this study reflect the success of employing parallel architectures to utilize the quad courses of the ARM processor on the target platform. The presented model can be an efficient medical assistant to provide automated detection and diagnosis for myopia ocular disease. Thus, it can be a promising healthcare toolkit that reduces the effort of the medical staff and increases the quality of the provided medical services for myopia patients

A Methodology and Open-Source Tools to Implement Convolutional Neural Networks Quantized with TensorFlow Lite on FPGAs

Convolutional neural networks (CNNs) are used for classification, as they can extract complex features from input data. The training and inference of these networks typically require platforms with CPUs and GPUs. To execute the forward propagation of neural networks in low-power devices with limited resources, TensorFlow introduced TFLite. This library enables the inference process on microcontrollers by quantizing the network parameters and utilizing integer arithmetic. A limitation of TFLite is that it does not support CNNs to perform inference on FPGAs, a critical need for embedded applications that require parallelism. Here, we present a methodology and open-source tools for implementing CNNs quantized with TFLite on FPGAs. We developed a customizable accelerator for AXI-Lite-based systems on chips (SoCs), and we tested it on a Digilent Zybo-Z7 board featuring the XC7Z020 FPGA and an ARM processor at 667 MHz. Moreover, we evaluated this approach by employing CNNs trained to identify handwritten characters using the MNIST dataset and facial expressions with the JAFFE database. We validated the accelerator results with TFLite running on a laptop with an AMD 16-thread CPU running at 4.2 GHz and 16 GB RAM. The accelerator’s power consumption was 11× lower than the laptop while keeping a reasonable execution time.