Arithmetic Devices Research Articles

An interconnect-free micro-electromechanical 7-bit arithmetic device for multi-operand programmable computing

Computational power density and interconnection between transistors have grown to be the dominant challenges for the continued scaling of complementary metal–oxide–semiconductor (CMOS) technology due to limited integration density and computing power. Herein, we designed a novel, hardware-efficient, interconnect-free microelectromechanical 7:3 compressor using three microbeam resonators. Each resonator is configured with seven equal-weighted inputs and multiple driven frequencies, thus defining the transformation rules for transmitting resonance frequency to binary outputs, performing summation operations, and displaying outputs in compact binary format. The device achieves low power consumption and excellent switching reliability even after 3 × 103 repeated cycles. These performance improvements, including enhanced computational power capacity and hardware efficiency, are paramount for moderately downscaling devices. Finally, our proposed paradigm shift for circuit design provides an attractive alternative to traditional electronic digital computing and paves the way for multioperand programmable computing based on electromechanical systems.

SYNTHESIS OF A TABLE-TYPE TONAL ARITHMETIC DEVICE

One of the obstacles to the further development of the capabilities of high-speed measuring technology is the limitations of digital electronics in terms of the ADC control circuit. The paper proposes to use an alternative approach based on arithmetic in the system of residual classes, while discrete phases of harmonic signals are used as the basis for coding modular numbers. Before a high-speed ADC control scheme is implemented, it is necessary to theoretically justify the functioning of basic computing devices. The article discusses algorithms for the operation of a tabular arithmetic device and a phased key with a high rate of state change. A simple model of the computational path is given in order to focus attention on possible problems with the microwave signal. Modern achievements in the field of potential semiconductor and superconducting instrumentation are analyzed.

DESIGN AND SYNTHESIS OF TERNARY LOGIC ELEMENTS

The aim of this paper is creating some ternary elements. The threshold element of ternary logic on bipolar transistors and elements of ternary systems based on it are considered. The main disadvantages of this approach are identified. The multi-threshold element of multivalued logic and its specific four-threshold implementation are considered. The scientific nowelty is the using of a multithreshold element of multivalued logic as a basis for constructing elements of ternary systems. It is shown that the advantages of a multi-threshold element of multi-valued logic are a larger number of thresholds of input signals, a larger number of levels that it can distinguish and a larger number of output signals. The implementation of some ternary elements, such as half-adder, disjunction and strong conjunction, is given. The practical significance of obtained results is that the multithreshold element of multivalued logic allows us to use it for synthesis basic elements of ternary logic and use one approach for all of them. Additional practical advantage is that in practice it allows you to build more diverse logical and arithmetic devices with a simplified implementation. The implementation of ternary devices based on threshold logic is a way to create ternary devices that can compete with binary devices in terms of equipment, capacity, operational capabilities, and variety. This, in turn, leads to greater speed and simplification of the structure of devices, as well as increasing the speed of data processing. These advantages are significant in such areas of computer use as intelligent data processing systems, expert systems, decision theory, i.e., where data analysis is performed. Prospects for further research are to use the method of construction and synthesis of nodes of ternary computer systems, based on MTEML. Their optimization, and development of principles of mathematical modeling and software of such systems and their elements is expedient.

About Possibilities of the Probabilistic Form of Information Representation in Military Computing Devices

At present, digital signal processing involves enormous amounts of computations with large-bit arrays, which are carried out in real time. In connection with the need to solve more and more complex problems, constantly growing requirements are imposed on the main parameters of digital processors (speed, reliability, power consumption, etc.), which determine the computing capabilities of systems with digital signal processing. In turn, the rapid development of microelectronics, its successes make it possible to create more and more high-performance computing systems, which makes it possible to solve more and more complex problems, including in the military sphere. The production of the latest information technology means is a technological task that can be solved exclusively by economically developed countries. Bringing domestic microelectronics to the current world level requires significant investments. Therefore, the study and research of discrete nodes and devices is of the direct practical importance. When developing promising computers, new technological approaches should be applied: minimizing power consumption, maintaining modularity and high computational density within a single node, creating high-speed data transmission with the lowest delays, creating an efficient storage system, and choosing the best types of memory. One of such possible approaches is the use of a non-positional form of information presentation in computing systems for national and military purposes. This gives a number of advantages, the main ones of which are: a decrease (by orders of magnitude) in the hardware volume of computing devices, an increase in the speed of calculations, an increase in the noise immunity of communication channels. To use the above method, it is proposed to include a probabilistic arithmetic device in the information processing device that performs basic arithmetic operations (addition, multiplication, exponentiation, subtraction, division), which are performed without the use of additional algorithms and mechanisms, in contrast to “classical" digital representation of binary information, where all operations are performed on the basis of the addition operation.

New Era of IoT Network Protection and PackagesThrough Prolonged Range

In this research mission, we motive to construct a protracted-variety (ProlongedRange)-primarily based net of factors (IoT) comfortable localization device and appliance primarily based totally on multisensory synthesiscomputation. The Prolonged range generation is used to layout a community security device and right now deal with the computing device, wherein the purpose is to broaden a community server host that collects and approaches function signals from the multisensingsignal series and evaluation processing module and at once detects region by using community nodes thru the sensors cloud, excessive-degree improvement platform, and the multisensory fusion computing workstations, which send the consequences to the crucial monitoring gadget thru the Wi-Fi gadgets of the Prolonged range network. The relaxed localization computing chip very final outcomes, as advanced on this mission, can be used in the domain names of electricity control, environmental manipulate, facts management, manufacturing unit monitoring, and renewable strength manipulate. The device of this task comprises prolonged range hosts, which get hold of signs from numerous nodes and are linked to multisensory fusion arithmetic device via a Wi-Fi network. To sum up, in this look at, we emphasize the usage of multisensory fusion computing generation to implement a relaxed localization gadget of a wireless sensor network technology (WSN), and we remember the use of the embedded system and prolonged range era to broaden a monitoring machine for manufacturing facility fire manage anti-theft, energy, facts, and protection primarily based on cozy localization. In this study, we pass domain names and integrate associated engineering automation, community safety technology, multisensory synthesis computation design, and the (ProlongedRange) localization method, and the study’sfindings are anticipated to make a contribution to the network protection of the protection organization and studies at theLora IoTlocalization method.

Synthesis of fast-operating devices for digital signal processing based on the number­theoretic transforms

The selection of special-form moduli and their corresponding primitive roots have been proposed, which provide for a simplified structure of arithmetic devices using number-theoretic transforms. A method for determining moduli has been developed that ensures a minimum number of arithmetic operations when performing the modulo addition and multiplication operations. The structures of special-form modulo adders have been developed and modeled, which make it possible to perform the addition operation as quickly as possible. The modulo adders for the Fermat, Mersenne, and Golomb numbers have been synthesized and tested, which could be used in the arithmetic units of high-speed correlators and filters. Real-time correlation and convolution calculation become a rather time-consuming task in the case of long input sequences. To solve this task, it is advisable to apply the so-called fast algorithms. However, this requires the high-performance calculators of convolution and correlation, which often exceed the capabilities of modern computer equipment, Therefore, the proposed procedure for determining the modulus, as well as the designed structural circuits for special-form modulo adders, make it possible to accelerate the computation of correlations and convolutions using number-theoretic transforms. Since the operation of modulo multiplication is performed using the addition and shift operations, the complexity of calculating the number-theoretic transformations largely depends on the number of unities in the binary representation of the degrees of the primitive root. The operation of multiplication is typically reduced to the multiple addition of numbers, which is why the complexity and speed performance of arithmetic devices for numeric-theoretic transformations is determined by the characteristics of the modulo adders. The proposed method for designing computing moduli for the digital devices that calculate correlation and convolution, based on rapid theoretical-numerical transformations, provides the simplified hardware and software implementation of these structures, resulting in high-speed processing of signals and images

Multi-input multiplexers and selectors as basic shifter blocks in arithmetic devices operating in floating point: comparative analysis

In case of the Field Programmable Gate Array implementation of arithmetic devices operating in floating point, the implementation of shifters is associated with some challenges. This work compares two approaches to the formation of basic shifter blocks: as selectors using carry chains and as multi-input multiplexers. Both approaches use exclusively a FPGA programmable logic. The work shows that basic blocks as multiplexers require more than twice fewer FPGA logic slices and are notable for 10-20% better performance when compared to those based on selectors.

CHARACTERISTICS OF DIGITAL AGC IN FIXED-POINT OPERATIONS

Introduction. Nowadays, communication systems are mostly digital. One of the tasks of automatic gain control in digital receivers is to maintain analog signals at the appropriately fixed level, which prevents saturation of the analogto-digital converter. Most numerical algorithms are based on floating point arithmetic, and digital automatic gain control is usually implemented using fixed-point arithmetic devices such as programmable logic chips and signal processors. As consequence of fixed-point arithmetic and hardware constraints usage, the out-put significant bits should be truncated correctly. Although many studies mention digital automatic gain control, its characteristics are not considered in detail in terms of the finite capacity of calculators.Objective. The purpose of the study is to analyze dynamic characteristics of digital automatic gain control implemented on a computer for operations on numbers with fixed-point.Materials and methods. Within the frames of the study in Matlab software was developed a mathematical model of digital automatic gain control. The model was implemented on a programmable logic chip.Results. The paper shows the difference in characteristics and features of the digital automatic gain control during operations on fixed-point numbers. The study provides the assessment of the effect of fixed-point signals on the stability of the digital automatic gain control and includes the analysis of causes of spurious oscillations of the control signal.Conclusion. The study proposes the algorithm for compensation of the control signal oscillations by means of correction of the reference level of the digital automatic gain control. Further is required to verify the proposed algorithm on real signals. The results of the study are relevant in development of digital receivers for communication systems of various purposes.

Analytical method for four wave mixing in space-frequency multiplexing optical fibers

In recent years, the transmission capacity of wavelength division multiplexing (WDM) communication systems has gradually approached to the nonlinear Shannon limit. To meet the increasing demand for communication capacity, space division multiplexing (SDM) has become one of the most concerned technologies. In this paper, the four-wave mixing process (FWM) in fibers is considered from the frequency domain to the mode division multiplexing (MDM) spatial domain under pump depletion and the exact analytical solution to the FWM coupled-mode equations in the space-frequency domain is in detail deduced. The analytical method is verified by numerically calculating the amplitude and phase evolution of the idler wave in non-degenerate four-wave mixing. We discuss three new applications of the analytical solution as follows. 1) Using the phase matching condition we select the terms in the multi-wave coupling equation, and only retain the coupling term that plays a major role. According to the analytical solution in this paper, the phase matching percentage parameter is introduced to determine the FWM coupling terms necessary for multi-wave coupling equations, thus simplifying the multi-wave coupling problem in the study. 2) Combining the analytical solution with the numerical calculation results, we find the initial phase relationship between the output idler and the input guided wave for phase-insensitive FWM, and we provide the analytical expression for a theoretical basis to efficiently design the FWM-based phase arithmetic devices in parallel operating at WDM and MDM systems. 3) We propose a nonlinear compensation algorithm based on analytical solution, which can be used in the few-mode transmission system. The algorithm can fast evaluate or compensate for the fiber nonlinearity by taking into account the pump depletion of the FWM effect. Compared with the traditional digital back propagation (DBP) algorithm, our algorithm has the advantage of lower complexity.

Principle and noise performance of optical phase arithmetic devices using four wave mixing

The existing theoretical equations cannot provide an excellent guidance for developing four-wave mixing (FWM)-based optical logic devices, though the experiments have been done in several researches. The optimization of noise figure performances of such devices should be further investigated. In the paper, the universal analytic expressions for the amplitude and phase of the idler in degenerate or non-degenerate FWM process under pump depletion are derived in detail from the nonlinear coupled-mode equations for guiding optical waves propagation in highly nonlinear fiber. The universal analytic expressions are obtained by the first-and the third-kind of elliptic integrals. By using equivalent infinitesimal to calculate the limit of phase sensitive amplification, we find out the initial phase relationship between the idler and the input guided wave for phase-independent amplification, which is crucially important for explaining the operating principles of the FWM-based adder and subtracter. As an example, the configuration of non-degenerate FWM-based hybrid arithmetic device with three logic functions of A+B-C, A+C-B, and B+C-A for QPSK signals is presented, and then the noise transfer characteristics in terms of signal-to-noise ratio (SNR) and error vector magnitude (EVM) are taken into account by adjusting the fiber length, input wavelength, and optical power. The calculation results show as follows. 1) This kind of arithmetic device has a noise figure of about 1.1 dB and an input SNR of more than 24 dB is necessary for the symbol error rate of 10-3 without forward error correction, corresponding to an output EVM of 23.2%. 2) The length of highly nonlinear fiber used in the hybrid arithmetic device may be taken flexibly, provided that the variation of FWM conversion efficiency is controlled in a range of 1 dB relative to the maximum, with an EVM fluctuation of less than for the idlers. 3) The hybrid arithmetic device has an operating optical bandwidth of about 16 nm for the SNR degradation of 1.3 dB. 4) The output EVM increases with the increase of input power, and the allowable input power should be no more than 100 mW for an input SNR of 28 dB, noting that the larger the input SNR, the higher the allowable input power is.

Мультифункциональные арифметические устройства в остаточных классах

Мультифункциональные арифметические устройства в остаточных классах

Analysis of logical-dynamic argument conversion processes in arithmetic devices of digital control systems

The procedure for analysis of logical-dynamic processes of argument conversion in arithmetic devices of digital control systems was developed. Disadvantages and limitations of the formal methods used to describe processes in control systems were described and a graph-analytical method for describing the processes of argument conversion was proposed. Analysis of the logical-dynamic processes of conversion of data arguments in adders and multipliers used in digital control systems was performed. Sign-positional notation makes it possible to significantly increase speed of adders and multipliers in digital control systems. In this case, a necessity of formation of scientifically substantiated analytical rules for conversion of logical arguments and functional structures through which they are implemented appears. The analytical description of the processes of conversion of information arguments in digital control systems allows one to form their mathematical models with increased technological and informational qualities as well as solve optimization problems. The summation process in arithmetic devices is realized in accordance with the logic of argument conversion of the ternary notation. The axioms of the ternary notation can serve as a theoretical basis of the process of summation of arguments implemented in the binary notation format. The proposed approach enables evaluation of speed of the performed arithmetic operations with the use of various digital codes and opens up the possibility of improving the methods and algorithms of data processing in digital control systems

All-optical approach for conversion of a binary number having a fractional part to its decimal equivalent to three places of decimal using single system optical tree architecture

Several optical methods have been proposed for implementation of all optical logic and arithmetic devices during the last few decades. In this regard, the role of optical tree architecture can be mentioned as an important approach for conversion of an optical data from binary to decimal and vice-versa. In this communication, the authors propose a new concept of conversion of a binary number having fraction (fractional value) to its equivalent decimal counterpart to any desired number of places after decimal using a single optical circuit with outputs rearranged. In this operation, optical tree and some nonlinear material based switches are used properly owing to their high speed.

New simulative studies on performance of semiconductor optical amplifier based optical switches like frequency converter and add-drop multiplexer for optical data processors

Optics has proved its successful role in parallel logic, arithmetic or algebraic operations. So many different methods on optical data processing were proposed and implemented in last few decades. For implementing the all optical logic and arithmetic devices it needs different types of encoding principle like, polarization encoding principle, frequency encoding principle, intensity encoding principle and phase encoding principle. As the frequency is the basic characteristics of light, so frequency encoding principle is the most reliable one among all other encoding principles. Currently frequency encoding technique is established as a promising one for all optical processing, as frequency of light does not change normally after reflection, refraction, absorption etc. Again Semiconductor optical amplifier (SOA) can be used for different successful frequency conversions. Here in this technique ‘1’ logic state is represented by a frequency ν2 then ‘0’ state is represented by another frequency ν1 instead of intensity variation. In this paper the authors describe the simulation study of the performances of SOA in various optical switches like frequency conversion and add-drop multiplexer.

The analysis of the equipment expenses for bit-serial arithmetic devices in golden 1-propotion numerical system

The expenses of the equipment comparative analysis is given at devices construction for bit-serial adding and subtraction in golden 1-propotion numerical system. It showed, that using of the complement codes with signs in any forms reduces the expenses of the equipment comparative to using minimizing forms of two's complement codes

Hippocampal Polysynaptic Computation

Neural circuitry is a self-organizing arithmetic device that converts input to output and thereby remodels its computational algorithm to produce more desired output; however, experimental evidence regarding the mechanism by which information is modified and stored while propagating across polysynaptic networks is sparse. We used functional multineuron calcium imaging to monitor the spike outputs from thousands of CA1 neurons in response to the stimulation of two independent sites of the dentate gyrus in rat hippocampal networks ex vivo. Only pyramidal cells were analyzed based on post hoc immunostaining. Some CA1 pyramidal cells were observed to fire action potentials only when both sites were simultaneously stimulated (AND-like neurons), whereas other neurons fired in response to either site of stimulation but not to concurrent stimulation (XOR-like neurons). Both types of neurons were interlaced in the same network and altered their logical operation depending on the timing of paired stimulation. Repetitive paired stimulation for brief periods induced a persistent reorganization of AND and XOR operators, suggesting a flexibility in parallel distributed processing. We simulated these network functions in silico and found that synaptic modification of the CA3 recurrent excitation is pivotal to the shaping of logic plasticity. This work provides new insights into how microscopic synaptic properties are associated with the mesoscopic dynamics of complex microcircuits.

ALL-OPTICAL APPROACH FOR CONVERSION OF A BINARY NUMBER HAVING A FRACTIONAL PART TO ITS DECIMAL EQUIVALENT AND VICE-VERSA

Optics is found as a very potential candidate in information processing and computing. Several all optical methods have been proposed for implementation of all optical logic and arithmetic devices during the last few decades. In this regard, the role of optical tree architecture can be mentioned as an important approach for conversion of an optical data from binary to decimal and vice-versa. In this communication, the authors propose a new concept of conversion of a binary number having some fraction (fractional value) to its equivalent decimal counterpart and its vice-versa. To perform this operation, optical tree and some nonlinear material based switches are used properly.

Arithmetic Device Based on Multiple Schottky-like Junctions

Photoelectrodes containing cadmium sulfide deposited as powders and crystalline thin layers combined with semi-solid ionic liquid electrolyte behave like Schottky photodiodes. Appropriate connection of these devices results in simple optoelectronic logic gates (AND, XOR) and enables construction of an optoelectronic binary half-adder.

Fast fault-tolerant adders

Several measures can be undertaken to achieve fault-tolerance of arithmetic devices. They differ in the level of hardware redundancy and the coverage of detectable faults. The discussion of the possible solutions for fast fault tolerant adders is given in the paper. The hardware complexity growth and latency overhead of various designs with respect to fault-coverage is discussed in the paper. It is shown that the designs of fast fault-tolerant adders based on the concept of residue code or double-rail code are preferable.

Automated design of modular arithmetic devices: Might CAD replace an engineer

The results of an experimental comparison of patented modular arithmetic circuits with logic circuits synthesized by means of automated design are presented. It is shown that the patented circuits have less constructive complexity.