Arithmetic Datapaths Research Articles

Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration

Deep learning applications have become ubiquitous in today’s era and it has led to vast development in machine learning (ML) accelerators. Systolic arrays have been a primary part of ML accelerator architecture. To fully leverage the systolic arrays, it is required to explore the computer arithmetic data-path components and their tradeoffs in accelerators. We present a novel factored systolic array (FSA) architecture, in which the carry propagation adder (CPA) and carry-save adder (CSA) perform hybrid accumulation on least significant bit (LSB) bits and most significant bits (MSB) bits, respectively, inside each processing element. In addition, a small CPA to complete accumulation for MSB bits along with rounding logic for each column of the array is placed, which not only reduces the area, delay, and power but also balances the combinational and sequential area tradeoffs. We demonstrate the hybrid accumulator with partial CPA factoring in “Gemmini,” an open-source practical systolic array accelerator and factoring technique does not change the functionality of the base design. We implemented three baselines, original Gemmini and two variants of it, and show that the proposed approach leads to overall significant reduction in area within the range 12.8% – 50.2% and in power within the range 18.6% – 41% with improved or similar delay in comparison to the baselines.

A survey of approximate arithmetic circuits and blocks

Abstract Approximate computing has become an emerging research topic for energy-efficient design of circuits and systems. Many approximate arithmetic circuits have been proposed, therefore it is critical to summarize the available approximation techniques to improve performance and energy efficiency at a acceptable accuracy loss. This paper presents an overview of circuit-level techniques used for approximate arithmetic. This paper provides a detailed review of circuit-level approximation techniques for the arithmetic data path. Its focus is on identifying critical circuit-level approximation techniques that apply to computational units and blocks. Approximate adders, multipliers, dividers, and squarer are introduced and classified according to their approximation methods. FFT and MAC are discussed as computational blocks that employ an approximate algorithm for implementation.

Framework-based Arithmetic Datapath Generation to Explore Parallel Binary Multipliers

Arithmetic modules usually have a significant impact on performance, circuit area, energy, and power in digital circuits of DSP (Digital Signal Processing). Exploring implementation trade-offs in these circuits is of utmost importance in low-power and low-cost devices such as sensors in IoT devices which often have stringent requirements. Multipliers are of particular concern due to their ubiquitous use in DSP algorithms and their inherent implementation complexity. This work proposes a framework to efficiently generalize and explore different compositions of arithmetic operators with an emphasis on parallel binary multipliers, guiding the designer through the micro-architecture development. Several partial product encoders were combined with multiple compression trees to generate multipliers that were synthesized in a commercial 65 nm to obtain area, power, and timing results.

Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths

With technology scaling leading to reliability problems and a proliferation of hardware accelerators, there is a need for cost-effective techniques to detect errors in complex datapaths. Modulo (residue) arithmetic is useful for creating a shadow datapath to check the computation of an arithmetic datapath and involves three key steps: 1) reduction of the inputs to modulo shadow values; 2) computation with those shadow values; and 3) checking the outputs for consistency with the shadow outputs. The focus of this paper is new gate-level architectures and algorithms to reduce the cost of modulo shadow datapaths. We introduce new low-cost architectures for the functional units performing the aforementioned reduction, shadow computation, and checking operations. We compare our functional units to the previous state-of-the-art approach, observing a 12.5% reduction in area and a 47.1% reduction in delay for a 32-bit mod-3 reducer; that our reducer costs, which tend to dominate shadow datapath costs, do not increase with larger modulo bases; and that for modulo-15 and above, all of our functional units have better area and delay than their previous counterparts. To demonstrate the cost-effectiveness of our approach in computation-intensive accelerator applications, we design custom pipelined shadow datapaths for five compound functional units implementing a variety of vector and matrix operations. For a 32-bit main datapath and 2-bit shadow datapath, we observe area costs of 6%–10% and reliability improvements against single event transient errors of 3–61 $\times$ . For an 8-bit shadow datapath, we observe area costs of 15%–20% and reliability gains of 121–2477 $\times$ .

Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra

Recent developments in formal verification of arithmetic datapaths make efficient use of symbolic computer algebra algorithms. The circuit is modeled as an ideal in polynomial rings, and Grobner basis (GB) reductions are performed over these polynomials to derive a canonical representation. As they model logic gates of the circuit, the ideals comprise largely of Boolean (or pseudo-Boolean) polynomials. This paper considers a logic synthesis analogue of GB reductions over Boolean polynomials, by interpreting symbolic algebra as the unate cube set algebra over characteristic sets. By representing Boolean polynomials as characteristic sets using zero-suppressed binary decision diagrams (ZDDs), implicit algorithms are efficiently designed for GB-reduction for datapath circuits. We show that the imposition of circuit-topology-based monomial orders exposes a special structure on the ZDD representation of the polynomials. The subexpressions employed in the GB-reduction are readily visible as subgraphs on the ZDDs, which are directly used to compose the result. Our division algorithms effectively cancel multiple monomials implicitly in one-step, simplify the search for divisors, and avoid intermediate size explosion. Experiments performed over various finite field arithmetic architectures demonstrate the efficiency of our algorithms and implementations; our approach is orders of magnitude faster as compared to conventional methods.

Adaptive Approximate Computing in Arithmetic Datapaths

Editor’s note: Approximate arithmetic units are used in error tolerant applications, like image processing, to minimize energy, and resource usage in general, by keeping accuracy to the minimum level required. However, in a datapath errors may accumulate over successive approximate operations. This article proposes a scheme to bound the size of the errors with adaptive error detection and correction as an integral part of the datapath. —Axel Jantsch, TU Wien

Formal Verification of Arithmetic Circuits by Function Extraction

This paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification, or to extract an arithmetic function implemented by the circuit. Experiments were performed on arithmetic circuits synthesized and mapped onto standard cells using ABC system. The results demonstrate scalability of the method to large arithmetic circuits, such as multipliers, multiply-accumulate, and other elements of arithmetic datapaths with up to 512-bit operands and over 2 million gates. The results show that our approach wins over the state-of-the-art SAT/satisfiability modulo theory solvers by several orders of magnitude of CPU time. The procedure has linear runtime and memory complexity, measured by the number of logic gates.

Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder

Objective: VLSI integer adders are critical elements in general purposed DSP and DSPA processors. These used in design of ALU, floating point arithmetic data paths and address generation units. Parallel prefix adders rely on simple cell design. Modern FPGAs utilize fast carry chain for optimization ripple carry adder. Methods/Analysis: Design of the delay models and cost analysis by VLSI embedded system is done in this paper. Prefix adder with reversible logic gates utilizing 16 bit kogge stone adder have been design using PERES logic. Findings: Methodology is based on the fact that a parallel prefix adder can be represented as a graph consists of carry operator nodes. The adder structure has minimum logic depth and binary tree structure with minimum fan-out. From the simulate results this is formed that computational path net delay for 16 X16 bit prefix adder using reversible logic is 20.828 ns with Kogge Stone Adder is reading to 17.247ns. Novelty/Improvement: The multiple based on 16 bit Kogge Stone Adder is formed to be less efficient than the case of reversible adder in term of delay and power analysis.

Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic

Binary addition is one of the primitive operations in computer arithmetic. High performance VLSI integer adders are critical elements in general purpose and digital-signal processing processors since they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. Speed, delay and area are the performance parameters for any adder. Speed can be achieved by means of Square Root Carry Select Adder (SQRT CSLA). Tradeoff between those parameters plays the major role in designing new architecture. From the structure of SQRT CSLA, there is a scope to reduce area by using Zero Finding Logic (ZFC) technique. By using ZFC technique in SQRT CSLA, 16bit architecture has been developed. The modified architecture has reduced area and power when compared to SQRT CSLA Adder. The adder is implemented on Spartan 3E FPGA and is compared with SQRT CSLA. Result analysis Show that the proposed adder gives reduced memory when compared to SQRT CSLA using ZFC.

A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors

Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented.

ICAT: Engine to Perform Range Analysis and Allocate Bit-Widths for Arithmetic Datapaths

Range analysis determines allocation of fixed-point integer bit-widths, which is critical for arithmetic on fixed-point representations. The traditional methods, either simulation-based or static, can be time-consuming and produce coarse bounds, potentially leading to large error bounds and unnecessary bits. In this paper, we propose a new static method to perform fixed-point range analysis towards obtaining the tighter ranges efficiently. The hybrid method, ICAT, combines four techniques, including Interval arithmetic, consistency checking, affine arithmetic and arithmetic transform and is the only method that is aware how far it is from the exact solution. For the benchmarks available with comparable methods, we show that the bit-width allocation can be obtained with better results, and in shorter execution time.

Exploring redundant arithmetics in computer-aided design of arithmetic datapaths

The rapid pace of technological evolution places a substantial amount of pressure on minimizing the time-to-market for integrated circuit designers. Such pressure on the design cycle combined with strict performance constraints makes the use of computer-aided design tools mandatory. In this context, CAD tools that improve performance in terms of delay, area or power consumption are of interest.In this paper, we present a design environment that is dedicated to arithmetic datapath design support. This environment consists of the following elements: (1) Stratus: a language that is dedicated to the parameterized generation of VLSI modules and that allows several levels of abstraction; (2) ArithLib: a library of parameterized arithmetic IP-block generators; and (3) several optimization algorithms that choose the best architecture for each arithmetic operator of a datapath, given an optimization goal. These algorithms consider binary arithmetic as well as redundant arithmetic, given the good intrinsic performance of redundant architectures. In addition, experimental results are presented.

Using Arithmetic Transform to Calculate Ranges of Arithmetic Datapaths

Range analysis is used to optimize circuits and to allocate the bit-width. In this paper we introduce a new and efficient static method to analyze the datapath represented by a polynomial, and compute the range for the datapath, then yield the smallest output bit-width. The method is based on Arithmetic Transform which can guarantee accuracy, and can explore polynomials with single or multiple word-level variables. The experiments show the tighter bounds than other recent static methods and significantly faster executions than simulation.

Designing Custom Arithmetic Data Paths with FloPoCo

Efficient implementation of basic, data-path circuit elements is of fundamental importance to achieving high performance in FPGA-based acceleration of scientific computing. This work presents a leading effort to automate the production of pipelined data-path circuits for implementing numerical functions.

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided.

Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra

This paper addresses simulation-based verification of high-level [algorithmic, behavioral, or register-transfer level (RTL)] descriptions of arithmetic datapaths that perform polynomial computations over finite word-length operands. Such designs are typically found in digital signal processing (DSP) for audio/video and multimedia applications; where the word-lengths of input and output signals (bit-vectors) are predetermined and fixed according to the desired precision. Initial descriptions of such systems are usually specified as Matlab/C code. These are then automatically translated into behavioral/RTL descriptions for subsequent hardware synthesis. In order to verify that the initial Matlab/C model is bit-true equivalent to the translated RTL, how many simulation vectors need to be applied? This paper derives some important results that show that exhaustive simulation is not necessary to prove/disprove their equivalence. To derive these results, we model the datapath computations as polynomial functions over finite integer rings of the form , where corresponds to the bit-vector word-length. Subsequently, by exploring some number theoretic and algebraic properties of these rings, we derive an upper bound on the number of simulation vectors required to prove equivalence or to identify bugs. Moreover, these vectors cannot be arbitrarily generated. We identify exactly those vectors that need to be simulated. Experiments are performed within practical computer-aided design (CAD) settings to demonstrate the validity and applicability of these results.

A Normalization Method for Arithmetic Data-Path Verification

We propose a normalization technique for verifying arithmetic circuits in a bounded model-checking environment. Our technique operates on the arithmetic bit-level (ABL) description of the arithmetic circuit parts and property. The ABL description can easily be provided by the front-end of a register transfer level property checker. The proposed normalization greatly simplifies the SAT instances to be solved for arithmetic circuit verification. Our approach has been successfully applied to verify the integer pipeline of an industrial microprocessor with advanced DSP capabilities.

Optimization of polynomial datapaths using finite ring algebra

This article presents an approach to area optimization of arithmetic datapaths at register-transfer level (RTL). The focus is on those designs that perform polynomial computations (add, mult) over finite word-length operands (bit-vectors). We model such polynomial computations over m -bit vectors as algebra over finite integer rings of residue classes Z 2 m . Subsequently, we use the number-theoretic and algebraic properties of such rings to transform a given datapath computation into another, bit-true equivalent computation. We also derive a cost model to estimate, at RTL, the area cost of the computation. Using the transformation procedure along with the cost model, we devise algorithmic procedures to search for a lower-cost implementation. We show how these theoretical concepts can be applied to RTL optimization of arithmetic datapaths within practical CAD settings. Experiments conducted over a variety of benchmarks demonstrate substantial optimizations using our approach.

Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing

This paper addresses the equivalence verification problem of register-transfer level (RTL) descriptions that implement arithmetic computations (such as add, mult) over bit vectors with finite widths. A bit vector of size represents integer values from 0 to 2m-1, implying that the corresponding integer values are reduced modulo 2m(%2m). This suggests that bit-vector arithmetic can be efficiently modeled as algebra over finite integer rings, where the bit-vector size (m) dictates the cardinality of the ring (Z2 m). This paper models the arithmetic datapath verification problem as the equivalence testing of polynomial functions from Z2 n 1timesZ2 n 2times...timesZ2 n drarrZ2 m. We formulate the equivalence problem into that of proving whether f-gequiv0%2m. Fundamental concepts and results from ldquonumber,rdquo ldquoring,rdquo and ldquoideal theoryrdquo are subsequently employed to develop systematic complete algorithmic procedures to solve the problem. We demonstrate the application of the proposed theoretical concepts to high-level (behavioral/RTL) verification of bit-vector arithmetic within practical computer-aided design settings. Using our approach, we verify a set of arithmetic datapaths at RTL, where contemporary verification approaches prove to be infeasible.

IBM PowerPC 440 FPU with complex-arithmetic extensions

The PowerPC® 440 floating-point unit (FPU) with complex-arithmetic extensions is an embedded application-specific integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene®/L compute chip. The FPU core implements the floating-point instruction set from the PowerPC Architecture™ and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions define double-precision operations that are primarily single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The PowerPC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.