Area Array Components Research Articles

Integral Plugged Blind via in Printed Wiring Boards

Adoption of fine pitch and high lead count area array components in high-reliability applications such as military and space electronics demands high-density interconnect (HDI) features in multilayer printed wiring boards (PWBs). Usage of cap-plated fine vias that are plugged with dielectric material is one of the approaches to meet the circuit density requirements. In this article, a novel method called “integral plugged blind via” without secondary processing steps, such as curing and planarization, is described to realize HDI multilayer PWBs. In this method, through vias are epoxy plugged during the lamination of inner layer circuits in vacuum-assisted hydraulic press cycle. Plugged blind vias are formed as an integral part of the fabrication process. It is observed that there is no excess ooze out of resin material from the blind vias in the laminated substrate and blind vias are found to have a negligible dimple and no voids. This is attributed to the gasket effect due to the elastomeric property of specialty release films, which conform (follow) to the contour of plated through vias during the vacuum lamination cycle. Plugged blind vias are subjected to critical thermomechanical stress to evaluate interconnection integrity. It is found that there is negligible change in the resistance of vias and resin plugged vias are free from defects such as barrel crack or knee crack of plated through hole (PTH) or delamination in the cured plugged material. Robustness of these resin-filled blind vias is attributed to anchored plated barrel with the additional support provided by plugged material, which restricts the thermomechanical deformation of plated copper.

Strength and Isothermal Fatigue Resistance of SnBi/SnAgCu Joints Reflowed at Low Temperatures

Abstract Soldered micro-electronics assemblies may have to survive a variety of mechanical loads in repeated drops, cyclic bending, or vibration. A very large body of work has addressed the isothermal fatigue performance of SnAgCu solder joints. This work offers a general assessment of the achievable performance of so-called hybrid solder joints formed by soldering with eutectic SnBi or SnBiAg to SnAgCu bumps on area array components. This allows for soldering at much lower temperatures than with SnAgCu alone, but the deformation and damage properties of the resulting structures depend strongly on details of the design and process. A peak reflow temperature of 175 °C was shown to be sufficient to ensure that the life of the joints remains limited by fatigue of the unmixed SnAgCu near the component. However, a higher effective stiffness of the mixed region near the substrate means that the life will be lower by 45%.

Recent progress on the development of Sn–Bi based low-temperature Pb-free solders

With the implementation of legislations on inhibiting the usage of Sn–Pb solder in consumer electronic products, Sn–Ag–Cu series solder has been gotten the most application. However, there are some stimulations from electronic manufacturers to adopt low temperature soldering such as the economic driver from the reduction in manufacturing assembly cost and the reliability driver to avoid the dynamic warpage of area array components caused from Sn–Ag–Cu solder. Sn–Bi series solder is one of the promising candidates, which met the requirements for low melting point, low cost and environment friendly. However, the disadvantage of brittleness characteristic prevented its wide practical application. In order to promote the better application of Sn–Bi based solders, many efforts have been made to improve the wettability, mechanical properties and reliability of Sn–Bi based solders. This paper will summarize the related results about Sn–Bi solder alloys from wettability, interfacial reaction, mechanical properties of Sn–Bi solder and reliabilities of Sn–Bi solder joints. Moreover, in order to improve the properties of Sn–Bi solders, researchers have done lots of works on effect of addition of element dopants. The corresponding works of effect of alloying elements on the properties of Sn–Bi solder were also focused. According to the existing research results, it provides an important basis of understanding the current development of Sn–Bi solders.

Effects of Solder Paste Volume and Reflow Profiles on the Thermal Cycling Performance of Mixed SnAgCu/SnPb Solder Joints

Manufacturers of most high-reliability microelectronics products are still exempt from the requirement to eliminate Pb from their soldering process, and neither their components nor their printed circuit boards can always survive a lead-free reflow profile. When faced with the need to incorporate a lead-free ball grid array or chip-scale package into one of their products, they are thus faced with three alternatives: attaching it separately using a rework station to establish a localized lead free profile; reballing the component with eutectic SnPb solder; or soldering it to the board with a eutectic SnPb solder paste to produce high-Sn joints with a few percent of Pb. Any of these approaches may affect the final reliability of the assembly in its own way, and comparisons between them by accelerated testing are confounded by very different acceleration factors. Optimization of solder paste volumes and reflow profiles for mixed soldering is of course less affected by this, but common experiences have been that optimized mixing requires a typical lead-free reflow profile. This clearly defeats the purpose of mixing in many cases. Two different sets of experiments were conducted to assess the consequences of soldering SnAgCu (SAC) balls with a eutectic SnPb paste for the thermal fatigue resistance of the resulting solder joints. The first experiment addressed effects of solder paste volume and common reflow profile alternatives. Based on the results of this, the second set of experiments involved the development of an improved low-temperature profile and the comparison of this with common SnPb and lead-free profiles in terms of thermal cycling performance. Five different high and moderate strain area array components were tested with SnPb, SAC, and mixed SAC/SnPb solder joints, and the results are discussed on the basis of known test parameter dependencies and trends. The improved profile was shown to optimize the performance of the mixed joints, but indications are that these may still compare poorly to pure eutectic ones for some components. All five components may have shorter lives with lead-free than with SnPb joints in service.

Rework of Lead-Free Area Array Packages Assembled on Ultrathin Flexible Substrates

The introduction of stacking technology has enabled the memory industry to cope with the continuous demand for higher performance and greater capacity. Among other variants of stacking, module-level stacking is gaining steady popularity and acceptance as an option to fulfill this need. One of the approaches for module-level stacking is to fold a double-sided flexible substrate-based assembly around a metal core. Carrying out rework on a flexible substrate poses several unique challenges. Moreover, the tightly spaced assembly of lead-free area array devices in module stacking further increases rework complexity. As a result, the rework process of area array devices assembled on flexible substrate needs to be carefully controlled. This paper describes the attempts to develop a process for reworking area array devices on ultrathin flexible printed circuit boards (PCBs) with a tight component-to-component spacing of 0.38 mm. The research addresses several different aspects related to the rework of area array components on an ultrathin flexible PCB. This paper has been divided into two sections. The first section deals with initial screening experiments which include designing a rework fixture, development of thermal profiles, and the selection of a site-redressing technique. The second section of this paper evaluates different reflow methods, namely a rework station and a convection oven. Locations of the rework devices as well as the options of component attachment methods are incorporated into the experimental design. Based on the experiments performed and results obtained, a recipe for successful rework is presented. The key concerns and observations related to the issues and challenges associated with the rework process are also presented.

Developing a Repeatable and Reliable Rework Process for Lead-Free Fine-Pitch BGAs

Area array components are increasingly used to miniaturize modern day circuitry. Assembling these surface-mount components using lead-free solder pastes has been the subject of interest for several years. Reworking a ball grid array (BGA) is complicated as the solder joints are hidden underneath the component. The process window to rework a BGA is narrow. There are several critical factors which complicate and affect the repeatability of the rework process. The objective of this research is to develop a reliable and repeatable process to rework lead-free fine-pitch BGAs. The process steps to rework a BGA are component removal, site redressing, solder paste/flux deposition, component replacement, and reflow. This study applied designed experiments to evaluate multiple alternatives for several rework process steps. Two alternatives for site redressing, namely copper wick with soldering iron and vacuum desoldering are evaluated. Similarly, the application of solder paste versus flux is compared. A localized reflow method at the rework machine is compared with solder reflow using a reflow oven. The pros and cons of using the two reflow methods and the effect of multiple reflow cycles on solder joint reliability is discussed. Nozzles with and without thermal shields were evaluated. A nozzle with deflectors on the outer side was found to work satisfactorily. Localized reflow in a semiautomated rework machine resulted in partial reflow of components adjacent to the reworked BGA. Thermal repeatability was also a concern. A 15degC drop in temperature was observed with the use of CoolCaps. The soldering iron with wick redressing method was less time consuming. Applying paste using a ministencil posed challenges due to lack of real-estate around the reworked BGA. A reliability study consisting of cross-sectional analysis, scanning electron microscopy (SEM), thermal shock, and thermal cycling were conducted to determine the reliability of the reworked solder joints. The copper wick with soldering iron method was favorable in terms of cycle time. The reflow oven is preferred as it avoids partial reflow of adjacent components. Localized reflow is effective when CoolCaps are used. The flux attachment process was easier as the real-estate around the reworked BGA is very limited. All the assemblies subjected to thermal shock and cycling passed the functional test.

Assembly issues with Sn/Ag/Cu bumped flip chips

PurposeThe objective of this research is to address issues that relate to the assembly of Sn/Ag/Cu bumped flip chips.Design/methodology/approachFlip chips bumped with Sn/Ag/Cu bumps were assembled onto different lead‐free surface finishes at lead‐free soldering temperatures. Sensitivity to fluxes, reflow profiles, pad finishes and pad designs were all investigated and the potential consequences for assembly yields were calculated numerically.FindingsSoldering defects, such as incomplete wetting and collapse and poor self‐centring were observed in the assemblies. Defect levels were sensitive to contact pad metallurgy and flux type, but not to flux level and reflow profile within the ranges considered. Owing to a particularly robust substrate‐pad design, defects observed in this work were limited to incomplete wetting and collapse, as well as poor self‐centering.Research limitations/implicationsThe scope of this work is limited to the lead‐free fluxes available at the time of research. A switch to lead‐free solder alloys in flip chip assemblies raises concerns with respect to the compatibilities of materials and the quality of soldering that is achievable. While this may be less of an issue in the case of larger area array components, such as ball grid arrays and chip scale packages, it is more of a concern for applications that use flip chips due to the smaller size of the solder spheres. Assembly yields tend to become more sensitive to the reduced collapse of the joints. More work is essential to investigate the potential benefits of more active lead‐free fluxes, both no‐clean tacky and liquid fluxes, in reducing or eliminating soldering defects.Originality/valueThe paper offers insights into assembly issues with Sn/Ag/Cu bumped flip chips.

Forward and Backward Compatibility of Solder Alloys With Component and Board Finishes

The primary objective of the research presented in this paper is to qualify the reliability of mixed assemblies by comparing them to the conventional Sn-Pb assembly and completely Pb-free assembly. The research investigates both forward and backward compatibility in electronic assemblies using a design of experiments (DOE) approach. The investigation utilized a test vehicle containing an area array component (BGA169) and chip components (0603 resistors). Hot air solder leveling (HASL) and organic solderability preservative (OSP) surface finishes were used on the test vehicles to represent Sn-Pb and Pb-free alternatives, respectively. The assembled test vehicles were cut into two panels - one containing a resistor section for isothermal aging and the other containing a BGA and another resistor section for thermal shock. The assemblies were subjected to isothermal aging and thermal shock tests as per Interconnecting and Packaging Electronic Circuits/Joint Electronic Device Engineering Council (IPC/JEDEC) standards. The resistors were sheared in the as-soldered condition, and at various isothermal aging intervals and thermal shock cycles. In order to simulate an intermetallic failure in isothermal aging, a reduced shear height (20 mum) was used for the shear test. The performance of the resistor solder joints were quantified in terms of the shear force. The performance of the ball grid array (BGA) solder joint during thermal shock testing was quantified in terms of the number of cycles to failure. Experimental results from shear analysis of resistor solder joints show that Pb-free alloy assemblies' performance is superior to those assembled using Sn-Pb alloy. Also, the ductile nature of the Sn-Ag-Cu (SAC) alloy provides the joints a better fatigue life. With the area array components, Pb-free assembly joints outlived the traditional Sn-Pb joints when subjected to thermal shock loading. Among the mixed assemblies, backward-compatible assemblies (Pb-free bumps and Sn-Pb solder alloy) showed superior performance. The microstructural analysis of the solder joints indicate a uniform distribution of lead in the solder joint matrix.

An experimental approach to characterize rate-dependent failure envelopes and failure site transitions in surface mount assemblies

This paper presents an experimental approach to identify the fatigue failure envelopes for solder damage in Printed Wiring Assemblies (PWAs) subjected to dynamic loading. An empirical, rate-dependent, power-law durability model, motivated by mechanistic considerations, is proposed to characterize the failure envelopes in terms of PWA flexural strain and strain rate, as damage metrics. It is further shown that there are critical combinations of these damage parameters, beyond which the failure site changes from the solder to other locations on the PWA. A case study, using a simple PWA specimen containing a single area array component, is presented to demonstrate the proposed approach. Under certain loading conditions, the failure site changes from the bulk solder to the Cu-trace/FR4 interface. The proposed durability model is shown to successfully describe the solder damage failure envelopes. The concept of a “Failure Map” is shown to provide a suitable framework to quantify the durability of the solder interconnect, determine its failure envelope, and identify the failure transition zone of the specimen. The applicability of the proposed technique for comparing the durability of different packaging styles and for developing design guidelines for PWAs subjected to dynamic loading (for example: drop) is discussed.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Effects of process conditions on reliability, microstructure evolution and failure modes of SnAgCu solder joints

In this study, microstructure evolution at intermetallic interfaces in SnAgCu solder joints of an area array component was investigated at various stages of a thermal cycling test. Failure modes of solder joints were analyzed to determine the effects of process conditions on crack propagation. Lead-free printed-circuit-board (PCB) assemblies were carried out using different foot print designs on PCBs, solder paste deposition volume and reflow profiles. Lead-free SnAgCu plastic-ball-grid-array (PBGA) components were assembled onto PCBs using SnAgCu solder paste. The assembled boards were subjected to the thermal cycling test (−40 °C/+125 °C), and crack initiation and crack propagation during the test were studied. Microstructure analysis and measurements of interface intermetallic growth were conducted using samples after 0, 1000, 2000 and 3000 thermal cycles. Failures were not found before 5700 thermal cycles and the characteristic lives of all solder joints produced using different process and design parameters were more than 7200 thermal cycles, indicating robust solder joints produced with a wide process window. In addition, the intermetallic interfaces were found to have Sn–Ni–Cu. The solder joints consisted of two Ag–Sn compounds exhibiting unique structures of Sn-rich and Ag-rich compounds. A crystalline star-shaped structure of Sn–Ni–Cu–P was also observed in a solder joint. The intermetallic thicknesses were less than 3 μm. The intermetallics growth was about 10% after 3000 thermal cycles. However, these compounds did not affect the reliability of the solder joints. Furthermore, findings in this study were compared with those in previous studies, and the comparison proved the validity of this study.

Mechanical cycling fatigue of PBGA package interconnects

Increased packaging density in micro-electronic products has advantaged attach of BGA, micro-BGA, CSP, and DCA packages. These area array packages are assembled to circuit boards that are reduced in size and thickness, by necessity. These assemblies would include flexible thin laminate circuit boards with area array components attached by solder balls. In normal use, these assemblies would be subjected to numerous ultra-low frequency mechanical deflections; consider a keypad when the user enters telephone numbers. Most of the reliability studies of area array packages have dealt with temperature cycling induced fatigue. However, less attention has been paid to mechanical bending fatigue of these packages. A test method has been developed to elucidate the mechanical bending fatigue issues of BGA, micro-BGA, CSP, and DCA packages attached to printed circuit boards. Appropriate bending fatigue reliability models and their theoretical basis are being developed. The test method and preliminary mechanical cyclic fatigue data on a PBGA package will be presented as a function of printed circuit board thickness. Consideration will be given to fatigue fracture morphology and its relation to solder joint location and rate of crack growth.

HDI substrate technology for electronic automotive applications

Presents a survey of build‐up technologies based on the manufacture of microvia in thin dielectric sheets (< 100µm) deposited on PWB materials. These technologies will permit the PWB industry to manufacture high density interconnect substrates and answer the routeing requirements of high number I/Os, BGAs and new area array components. Bull Electronics Angers (BEA) has developed an HDI technology where microvias with hole diameters lower than 100µm are mechanically or laser drilled and interconnected lines at pitch down to 200µm are manufactured. In the frame of a European MEDEA project, ATEMAES, the design of an electronic subsystem manufactured by Magnetti Marelli in ceramic thick film technology has been adapted to the design rules of the HDI technology developed by Bull. This is part of an evaluation program for the use of HDI technology for automotive applications.

Novel techniques for electronic component removal

Component removal for rework and repair is traditionally achieved by re‐melting of the solder, but the exposure of the assembly or its component parts to repeated soldering/ desoldering cycles may cause both immediate damage and create a significant long term reliability hazard. Rework is labour intensive and requires skilled operators. Area array components further increase the complexity of the rework process because of the number and inaccessibility of the solder joints. There is a growing requirement to recycle/reclaim electronic waste, creating the need for an effective process for dismantling of printed circuit board assemblies (PCBAs). This paper will present a brief review of alternative non‐thermal techniques for rework or dismantling of conventional soldered assemblies, including both chemical etchants and mechanical techniques. Results will then be presented on trials of chemical etchants, where rates of solder removal consistent with realistic times for component removal have been readily achieved using commercially available tin‐lead strippers. Electrochemical techniques are also shown to be usable in specific applications, i.e. where electrical contact can be readily made to the solder joints to be removed, and have the advantage of reclaiming the removed solder directly from the electrolyte.

Assembly of planar array components using anisotropic conducting adhesives-a benchmark study: II. Theory

This paper presents new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 /spl mu/m pitch area array component using anisotropic conductive adhesive (ACA) materials. This experimental configuration has features of micro ball grid array (/spl mu/BGA), chip scale packaging (CSP), and also flip-chip and conventional ball grid array (BGA) package structures. A range of materials combinations have been evaluated, including (random filled) adhesive materials based on both thermoplastic and thermosetting resin systems, combined with both organic and thick-film on ceramic substrate materials. The ACAs used have all been applied as films, and hence are also known as anisotropic conducting films (ACF). The test assemblies have been constructed using a specially developed instrumented assembly system which allows the measurement of the process temperatures and pressures and the consequent bondline thickness reduction and conductivity development. The effects of the process parameters on the resulting properties, particularly conductivity and yield, are reported, A complementary paper indicates the results of computational fluid dynamics (CFD) models of the early stages of the assembly process which allow the extrapolation of the present results to finer pitch geometries.

Assembly of planar array components using anisotropic conducting adhesives-a benchmark study: pt.I. Experiment

This paper presents new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 /spl mu/m pitch area array component using anisotropic conductive adhesive (ACA) materials. This experimental configuration has features of micro ball grid array (/spl mu/BGA), chip scale packaging (CSP), and also flip-chip and conventional ball grid array (BGA) package structures. A range of materials combinations have been evaluated, including (random filled) adhesive materials based on both thermoplastic and thermosetting resin systems, combined with both organic and thick-film on ceramic substrate materials. The ACAs used have all been applied as films, and hence are also known as anisotropic conducting films (ACF). The test assemblies have been constructed using a specially developed instrumented assembly system which allows the measurement of the process temperatures and pressures and the consequent bondline thickness reduction and conductivity development. The effects of the process parameters on the resulting properties, particularly conductivity and yield, are reported, A complementary paper indicates the results of computational fluid dynamics (CFD) models of the early stages of the assembly process which allow the extrapolation of the present results to finer pitch geometries.

Design Factors With Realistic I/O Distributions

This paper explores some design factors, including wireability, of packages in which the number of I/O per module to be interconnected varies widely. This is of interest because it is common for memory card designs and for work station and personal computer printed circuit designs. Memory cards often have a few relatively high pin count control logic modules supporting many low pin count array modules. Work station and personal computer cards often use low density “glue” logic modules with a few microprocessor modules and their high function supports. Printed circuit cost and performance factors are examined by example. Differences between area array and perimeter escape components and leverage possibilities of multi-chip modules are examined. A background tutorial on wireability analysis is given. The algorithm used was developed by Wadie Mikhail several years ago. Analyses are based on the length of wire paths available in a given design, the length of wire needed and the utilizations of the available paths. Utilization guidelines are suggested. Alternative wireability algorithms are identified and briefly discussed. Although the examples are given for cases of modules on cards, the methodologies and general conclusions are valid at other packaging levels; for example, for chips on multi-chip modules.