Architecture Partitioning Research Articles

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

Increased capabilities such as recognition and self-adaptability are now required from IoT applications. While IoT node power consumption is a major concern for these applications, cloud-based processing is becoming unsustainable due to continuous sensor or image data transmission over the wireless network. Thus optimized ML capabilities and data transfers should be integrated in the IoT node. Moreover, IoT applications are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). Thus, the versatility of the node is key in addressing this wide diversity of energy and processing needs. This paper presents SamurAI, a versatile IoT node bridging this gap in processing and in energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with a 207ns wake-up time optimized for sporadic computing, while OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) for more complex tasks up to 36GOPS. This architecture partitioning achieves best in class versatility metrics such as peak performance to idle power ratio. On an applicative classification scenario, it demonstrates system power gains, up to 3.5x compared to cloud-based processing, and thus extended battery lifetime.

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power, area, and timing costs. This article presents a systolic many-tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of conventional DFEs with no performance loss. A nine-tap configuration is demonstrated in a 112-Gb/s analog-to-digital converter (ADC)-digital signal processing (DSP) four-level pulse amplitude modulation (PAM-4) LR wireline receiver implemented in 7-nm FinFET. The architecture partitions the received signal into overlapping but computationally independent blocks thereby breaking the feedback loop of the DFE and allowing logic pipelining. Unlike existing feedback-breaking techniques, the computational overhead of the SB-DFE can be made arbitrarily small for any tap count—indeed, we show the practicality of SB-DFE implementations exceeding 30 taps. Optimized pipeline cuts are employed to minimize the latency through the SB-DFE while maintaining timing margin. The nine-tap SB-DFE is paired with a five-precursor tap feedforward equalizer (FFE) and compared to a two-tap-DFE 15-tap-FFE reference DSP implemented in the same receiver. A bit error rate of 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> is measured over a 36-dB loss channel—at least an order-of-magnitude reduction compared to the reference DSP. Power is reduced by 0.33 pJ/b. DSP gate area is reduced by 30%. Noise tolerance is improved by 0.2-mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> . Error-free operation is demonstrated on an RS(544,514) KP4 forward error correction (FEC)-encoded link even when the DFE tap values are manually stressed. Techniques for further reduction in complexity are described.

On tower and checkerboard neural network architectures for gene expression inference

BackgroundOne possible approach how to economically facilitate gene expression profiling is to use the L1000 platform which measures the expression of ∼1,000 landmark genes and uses a computational method to infer the expression of another ∼10,000 genes. One such method for the gene expression inference is a D–GEX which employs neural networks.ResultsWe propose two novel D–GEX architectures that significantly improve the quality of the inference by increasing the capacity of a network without any increase in the number of trained parameters. The architectures partition the network into individual towers. Our best proposed architecture — a checkerboard architecture with a skip connection and five towers — together with minor changes in the training protocol improves the average mean absolute error of the inference from 0.134 to 0.128.ConclusionsOur proposed approach increases the gene expression inference accuracy without increasing the number of weights of the model and thus without increasing the memory footprint of the model that is limiting its usage.

High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1

Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne, and space-borne imagers have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of gigapixel per second. This competes with limited on-board resources and bandwidth, making hyperspectral image compression a mission critical on-board processing task. At the same time, the “new space” trend is emerging, where launch costs decrease, and agile approaches are exploited building smallsats using commercial-off-the-shelf (COTS) parts. In this contribution, we introduce a high-performance parallel implementation of the CCSDS-123.0-B-1 hyperspectral compression algorithm targeting SRAM field-programmable gate array (FPGA) technology. The architecture exploits image segmentation to provide the robustness to data corruption and enables scalable throughput performance by leveraging segment-level parallelism. Furthermore, we exploit the capabilities of a COTS FPGA system-on-chip (SoC) device to optimize size, weight, power, and cost (SWaP-C). The architecture partitions a hyperspectral cube stored in a DRAM framebuffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. A 5-core implementation demonstrated on a Zynq-7045 FPGA achieves a throughput performance of 1387 Msamples/s [22.2 Gb/s at 16 bits per pixel per band (bpppb)] and outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors.

Decentralized Signal Detection via Expectation Propagation Algorithm for Uplink Massive MIMO Systems

The existing centralized antenna array architecture and the corresponding centralized baseband processing based signal detection algorithms incur huge burden on the raw baseband data rates and chip input/output bandwidth for massive multiple-input multiple-output (MIMO) systems. In this paper, we propose a novel decentralized baseband processing based signal detection under the framework of the expectation propagation algorithm (EPA) for uplink massive MIMO systems. This architecture partitions the base station antennas into multiple independent antenna clusters, each associated with analog and digital modulation circuitry, independent radio-frequency chains, and computing hardwares. The antenna clusters only access local channel state information and require low communication bandwidth. In the proposed scheme, the decentralized processing unit executes local channel estimation and signal detection, and delivers the partial message to the centralized processing unit parallelly, where the message contains the local means and variances iteratively updated by the EPA detector from each antenna cluster. The centralized processing unit operates the message fusion based on the proposed message fusion rule for decoding operation. Simulation results illustrate that the proposed decentralized EPA signal detection approaches the conventional centralized one with marginal computational complexity overhead when the number of antenna clusters is small, and outperforms the state-of-the-art decentralized counterparts.

TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs

Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like high density, high bandwidth, and low-power consumption. However, many defects in TSV are evolved during the fabrication and bonding process. In practice, faulty TSVs tend to be clustered. Employing spare TSVs (s-TSVs) is an acceptable method for repairing faulty TSVs. This article introduces a tree-based TSV repair framework to utilize hardware resources more efficiently for a higher repair rate. The proposed architecture partitions the s-TSVs for a different level of redundancy sharing. Experimental results show that the proposed design consumes 11.01 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area per signal TSV to achieve 99.99% yield for 0.05% failure rate. The proposed architecture also exhibits a higher repair rate of 73.33% for heavily clustered faults. Moreover, for the same number of functional and s-TSVs, the proposed approach reduces the delay overhead efficiently compared to the prior works.

Wideband Modeling of Power SiC mosfet Module and Conducted EMI Prediction of MVDC Railway Electrification System

The SiC mosfet in the medium-voltage direct-current (MVdc) transportation electrification system features faster switching performance, while simultaneously binging more significant electromagnetic interference (EMI) issues within the rolling stocks, substations, and radiated disturbance into space along the catenaries and tracks. Due to the necessity to involve both the transient characteristics of power semiconductor devices and the stray parameters of all the equipment in the analysis of EMI, it is considerably challenging to perform wideband device-level simulation on traditional commercial software for such a complex system with numerous trains and stations. A computationally efficient method for wideband modeling and simulation of the MVdc high-speed railway system for the assessment of conducted EMI during the project design stage is proposed in this article. Physical characteristics of the semiconductor devices, parasitic parameters of the mosfet package, and converter topology are all taken into consideration to provide not only accurate system-level performance of the system but also an insight into high-frequency characteristics under different operation conditions. The calculation burden is alleviated by a hierarchical circuit partitioning architecture based on the frequency-dependent time-domain transmission line model and the Norton equivalent parameter extraction of each mosfet module to split the whole system into several smaller subcircuits in terms of matrix size, and a fully parallel implementation of the MVdc system is carried out on the graphics processor. The developed program is used to study the case of Jing–Zhang high-speed railway system topology, which is compatible to be modified to the MVdc project. Simulation results show that it is essential to estimate the EMI level comprehensively considering the alternative of speed and dc voltage.

Architectural partitioning and deployment modeling on hybrid clouds

SummaryThe hybrid cloud idea is increasingly gaining momentum because it brings distinct advantages as a hosting platform for complex software systems. However, there are several challenges that need to be surmounted before hybrid hosting can become pervasive and penetrative. One main problem is to architecturally partition workloads across permutations of feasible cloud and non‐cloud deployment choices to yield the best‐fit hosting combination. Another is to predict the effort estimate to deliver such an advantageous hybrid deployment. In this paper, we describe a heuristic solution to address the said obstacles and converge on the ideal hybrid cloud deployment architecture, based on properties and characteristics of workloads that are sought to be hosted. We next propose a model to represent such a hybrid cloud deployment and demonstrate a method to estimate the effort required to implement and sustain that deployment. We also validate our model through dozens of case studies spanning several industry verticals and record results pertaining to how the industrial grouping of a software system can impact the aforementioned hybrid deployment model. Copyright © 2017 John Wiley &amp; Sons, Ltd.

Threshold based Routing Protocol for WSN with Sleep/Awake Scheduling

routing architecture partitions the whole network in to a group of cluster and only cluster head is responsible for forwarding the data to base station. In this work, we have considered the concept of heterogeneity as in Stable Election Protocol (SEP). In heterogeneous environment, a percentage of the population of sensor nodes is equipped with additional energy resources—this is a source of heterogeneity which may result from the initial setting or as the operation of the network evolves. SEP does not consider the residual energy of a node while electing cluster head to increase reliability as well as there is no concept of sleep nodes to enhance network lifetime. In this paper, we have proposed a routing protocol which will consider the residual energy of a node before making cluster head as well as we have introduced the concept of sleep nodes, so that it will be reliable and energy efficient and results will be compared with existing routing protocol of same category such as SEP. Keywordswireless sensor network, SEP, energy efficient, reliable

멀티코어 기반 파티셔닝 운영체제를 이용한 분산 복구 블록 설계 기법 및 응용

최근 항공기, 자동차와 같은 시스템들은 크기, 무게, 전력 등의 문제로 기존 연합형(Federated) 구조에서 모듈형(Modular) 구조로 개발되는 추세이며, 단일 하드웨어에 파티션 개념을 적용하여 다수의 논리적 노드들을 운용할 수 있는 파티션 운영체제도 등장하고 있다. 분산 복구 블록은 실시간 시스템에 적용 가능한 소프트웨어 결함 허용 기법으로 다수의 물리적 노드들을 동기화 시켜 동작시킴으로써 실시간 절체가 가능하도록 하는 설계 기법이다. 분산 복구 블록은 노드들 간의 실시간 동기화를 필요로 하기 때문에 단일 코어 기반의 파티션 구조에는 적합하지 않으며, 적용을 위해서는 멀티코어를 기반으로 하고 또한 AMP(Asymmetric Multi-Processing) 방식을 이용한 파티션 구조에 적용되어야 한다. 본 논문에서는 멀티코어 기반 supervised-AMP 가상화 방식의 파티션 운영체제를 이용한 분산 복구 블록 설계 기법을 제안한다. 또한 제안된 설계 기법의 유용성을 보이기 위하여 항공기용 비행제어시스템 시뮬레이션을 이용한 사례 연구를 보인다. Recently, embedded systems such as aircraft and automobilie, are developed as modular architecture instead of federated architecture because of SWaP(Size, Weight and Power) issues. In addition, partition operating system that support multiple logical node based on partition concept were recently appeared. Distributed recovery block is fault tolerance design scheme that applicable to mission critical real-time system to support real-time take over via real-time synchronization between participated nodes. Because of real-time synchronization, single-core based computer is not suitable for partition based distributed recovery block design scheme. Multi-core and AMP(Asymmetric Multi-Processing) based partition architecture is required to apply distributed recovery block design scheme. In this paper, we proposed design scheme of distributed recovery block on the multi-core based supervised-AMP architecture partition operating system. This paper implements flight control simulator for avionics to check feasibility of our design scheme.

An Optimized Hierarchical Cache Design Based on Data Access Features

As more cores are integrated into one die,chip multiprocessors suffers higher on-chip communication latency,and linearly increased directory overheard.Hierarchical cache architecture partitions on-chip caches into multilevel regions recursively,reducing the communication latency by replicating the data blocks to multiple regions that contains the requestor and alleviating the storage overhead of directory by using multilevel directory.According to the data distribution in the last-level cache,we improve the data placement policy and propose an enhanced hierarchical cache directory(EHCD).EHCD directly puts an incoming off-chip data block into the lowest region that contains the requestor to reduce access latency,which guarantees only one data replica is kept in the last-level cache for private data.EHCD improves the capacity utilization of the last-level cache as well as good scalability.Simulation results on a 16-core CMP show that compared with shared organization,EHCD gets 24% execution time reduction,and 15% reduction over original hierarchical cache design.

Systems of systems and coordinated atomic actions

System of systems (SoS) is an emerging field in the design and development of complex systems that are built from large scale component systems. A SoS has the following attributes: operational and managerial independence of components, a geographic extent that limits control mechanisms to information exchange, an evolutionary nature, and emergent behavior. The subsystems that comprise the SoS often are built by different organizations with conflicting goals, designed under different assumptions and built to different quality standards. These factors impact fault detection, fault isolation, and fault tolerance and can result in systems that cannot easily be debugged, integrated, or maintained. When fault detection and fault tolerance are deficient, the system may behave in a fragile or brittle manner, randomly and repeatedly crashing. Crashes prevent automated diagnosis algorithms from being executed and can prevent manual root cause analysis by erasing system state. Fragility during system integration can prevent achieving schedule milestones and deadlines. Deficient fault detection and fault isolation also impacts end users and system maintainers. (Think &lt;insert name of infamous project here&gt;).From the system architect's point of view, designing a system that can detect all possible fault conditions across all components can be an extremely difficult, if not impossible challenge. Can any system be trusted to diagnose or repair itself when it has been corrupted by faults? How do you prevent local faults from growing into global failures? The end users may have unreasonable expectations about how the system should behave when components within the SoS behave abnormally or fail. They may expect better behavior than the typical PC. The system maintainers may expect a coherent systems view of failures to isolate faulted components and to provide an orderly and safe shutdown or recovery.(Think power grid blackouts, Telecomm failures, etc.)The most beneficial way to achieve fault tolerance is to design in fault detection and fault reporting such that defined boundaries such as subsystems serve as natural firewalls for fault containment. Although partitioning the system into subsystems for fault containment is well known and practiced, the end result as experienced at the time of system integration is rarely a success. COTS middleware, intended to aid distributed design often becomes in effect a step backwards by providing fertile ground for faults and failures that breach fault containment boundaries. (Think &lt;insert name of OS or middleware vendor here&gt;)What can be done to improve this situation? This paper addresses the system architectural partitioning concept of the Coordinated Atomic Actions (CAA). CAA promotes a different manner of organizing software architecture that improves fault containment across potentially faulty components. CAA was first invented by members of Brian Randell's research group at the University of Newcastle at Tyne in the mid 1990's. CAA promotes the concept of the "transaction" which has been traditionally identified with database applications. When you access your bank account via ATM, you are exercising database transactions within your bank's financial SoS. CAA applies transactions to cooperating concurrent distributed processes, which are the basis for most large complex computing systems.

Implementation aspects of a low‐power AMLCD single chip

Abstract— Mobile phones are always in the operating mode; therefore, a continuous key focus during chip‐set design is low power. To achieve a low‐power display module, the drive scheme and the appropriate IC architecture must be carefully selected to accommodate the different modes of operation found in a typical handheld device. A chosen drive scheme and detailed description of the architecture partitioning, key element design such as a DC/DC converter, D/A selection, and RAM arbiter demonstrates how careful design choices lead to power‐optimized system solution.

Biomass Partitioning and Root Architecture Responses of Loblolly Pine Seedlings to Tillage in Piedmont and Coastal Plain Soils

Abstract In the southeastern United States, site preparation methods often involve surface and subsurface tillage used singly or in combination. However, growth responses to these treatments are often inconsistent across sites and physiographic regions. In an effort to gain insight into how pine growth is affected by tillage, the effects of two treatments, machine planting and combination tillage (i.e., disking, subsoiling, and bedding), were examined in terms of biomass partitioning and root system architecture of loblolly pine seedlings (Pinus taeda L.) on Piedmont and Upper Coastal Plain sites in Alabama and Georgia. Our objectives were to evaluate the effects of combination tillage on root system development and examine whether potential effects were related to aboveground measures. Seedling allometry indicated that for all sites and both physiographic regions, machine planting and combination tillage treatments resulted in similar biomass partitioning above- and belowground. Furthermore, on both Piedmont and Coastal Plain sites, root architecture was primarily influenced by the presence of the subsoil “rip” regardless of treatment. These conclusions suggest that compared to machine planting, combination tillage did not affect biomass partitioning on the functional rooting zone of these young pines to a degree that was biologically significant. South. J. Appl. For. 28(2):76–82.

40-43-gb/s oc-768 16:1 MUX/CMU chipset with SFI-5 compliance

In this paper, we present two copackaged ICs that provide complete OC-768 16:1 multiplexer (MUX) and clock multiplying unit (CMU) functionality. The 17-input 2.5-2.68-Gb/s parallel interface is Serdes Framer Interface Level 5 (SFI-5) compliant while the 40-43-Gb/s output satisfies OC-768 jitter generation specifications with 7 dB of margin. The system architecture and two-chip partitioning are discussed, followed by descriptions of the design challenges including SFI-5 compliance, 40-Gb/s MUX timing, and 20-GHz clock generation. A novel technique for stabilizing timing margins in the final high-speed multiplexer stage using in-phase and quadrature clocks is also presented. This chipset accommodates 11 bits of static skew and 21 bits of dynamic wander at the SFI-5 interface, while generating 125 fs rms of random jitter and 3.1 ps peak-to-peak of deterministic jitter at its 40-43-Gb/s outputs. The measured bit-error ratio is less than 10/sup -15/ for 2/sup 31/-1 PRBS data and is measurement time limited. The two chips occupy 15.6 mm/sup 2/ and 8.25 mm/sup 2/ of die area. Both are implemented in a 120-GHz f/sub T/ SiGe BiCMOS process.

Spatial Patterning and Social Complexity on Prehistoric Anatolian Tell Sites: Models for Mounds

The “tell” is one of the most recognizable features in the Near Eastern landscape. Its complicated stratigraphy signifies the long history of human habitation through the deposition of successive strata of occupation detritus. This study focuses on the organization of domestic architecture on Anatolian mounds from a diachronic perspective. Of particular interest is the observable metamorphosis in spatial patterning of domestic architecture concomitant with the stages of increasingly complex society. Although recent work contains numerous models applicable to prehistoric domestic architectural remains, including those treating greater societal complexity, the data used to generate these models have generally been derived from nonmounded settlements. Therefore, current theoretical frameworks must be reevaluated in order to render them effective in the analysis of architectural remains from tell sites. The domestic architecture on tell sites is examined using three types of spatial patterning analysis: increasingly complex task performance and the associated architectural partitioning of structures; access analysis; and issues of privacy and territoriality. These analytical methods, all interrelated, bear specifically on the physical structure (spatial patterning) of domestic tell architecture as residents experience socioeconomic change.

High-speed Si/SiGe technology for next generation wireless system applications

Si/SiGe integrated circuit technology represents a revolutionary opportunity to combine high-performance digital, analog, and rf circuits on a common substrate. The outstanding high-frequency performance of the Si/SiGe devices, combined with the high levels of integration of complementary metal–oxide–semiconductors will contribute to a long-term “paradigm shift” in the architectural partitioning of high-frequency high-performance wireless systems. This article outlines the key future systems applications for the technology.

Aboveground biomass partitioning and crown architecture of &lt;I&gt;Eucalyptus nitens&lt;/I&gt; following green pruning

Aboveground biomass partitioning and crown architecture of &lt;I&gt;Eucalyptus nitens&lt;/I&gt; following green pruning

RASSP Enterprise Technologies for SignalProcessor Life-Cycle Support

Enterprise integration technologies are a key contributor to improving time-to-market, cost, and design quality by a factor, which is the goal of the DARPA Rapid Prototyping of Application-Specific Signal Processors (RASSP) program [1]. The Lockheed Martin Advanced Technology Laboratories (ATL) RASSP team developed a productivity improvement model, shown in Fig. 1, that indicates the relative contributions of various RASSP technologies to the overall improvement. Enterprise technologies address the entire 17% enterprise partition, and more than half of the 30% reuse and model-year architecture partition, thus accounting for at least 35% of the overall RASSP productivity improvement. The ATL RASSP approach to implement enterprise systems is to extend commercial technologies so the results are available to a broad base of potential users. Unlike current automation concepts which start at later stages of the development cycle, the RASSP enterprise system supports the entire signal processor life cycle. Core concepts of the enterprise system include: Tools and tool frameworks integrated into an enterprise environment Program execution control through workflows Integrated data management functions Design reuse Concurrent engineering team support Integrated design engineering and manufacturing. The model-year architecture, which enables users to rapidly, efficiently upgrade systems with new technology, is supported in the enterprise system by a robust reuse management system. Manufacturing interface and communication services elements of the enterprise system provide improved concurrent engineering support for distributed product teams. The enterprise system will be provided to commercial and aerospace users as products, including a reusable set of workflows for electronics design, commercial tools supporting the enterprise system environment, and utilities to enable users to customize the RASSP enterprise system for a particular organization or project. The enterprise system development cycle includes four build cycles with increasing capabilities. The ATL team completed the Build 2 implementation in May‘96. This implementation supports the processes associated with detailed hardware/software design, architecture design, and trade-off analyses. It is being used at Lockheed Martin and multiple government sites for benchmarking and evaluation. Results to date indicate >5:1 productivity improvements in the manufacturing interface, and 5–10% improvements in design engineering, which is growing with increasing level of utilization.

Escrow techniques for mobile sales and inventory applications

We address the design of architectures and protocols for providing mobile users with integrated Personal Information Services and Applications (PISA), such as personalized news and financial information, and mobile database access. We present a system architecture for delivery of PISA based on replicated distributed servers connected to users via a personal communications services (PCS) network. The PISA architecture partitions the geographical coverage area into service areas, analogous to PCS registration areas, each of which is served by a single local server. When a user moves from one service area to another, the service is provided by the new local server. This is accomplished by a service handoff, analogous to a PCS call handoff, which entails some context information transfer from the old to the new server. We focus on the mobile sales and inventory application as an example of a PISA with a well-defined market segment. We design a database management protocol for supporting both mobile and stationary salespersons. Our design uses the site-transaction escrow method, thus allowing faster responses to mobile clients, minimizing the amount of context information which must be transferred during a service handoff, and allowing mobile clients to operate in disconnected mode by escrowing items on their local disks. We develop a formal model for reasoning about site-transaction escrow, and develop a scheme for performing dynamic resource reconfiguration which avoids the need for time-consuming and costly database synchronization operations (i.e., a two-phase commit) when the mobile sales transaction completes. A further refinement to the scheme avoids an n-way two-phase commit during resource reconfiguration operations, replacing it with several simpler two-phase commits.