Modern Computer Architectures Research Articles

On a Simplified Approach to Achieve Parallel Performance and Portability Across CPU and GPU Architectures

This paper presents software advances to easily exploit computer architectures consisting of a multi-core CPU and CPU+GPU to accelerate diverse types of high-performance computing (HPC) applications using a single code implementation. The paper describes and demonstrates the performance of the open-source C++ matrix and array (MATAR) library that uniquely offers: (1) a straightforward syntax for programming productivity, (2) usable data structures for data-oriented programming (DOP) for performance, and (3) a simple interface to the open-source C++ Kokkos library for portability and memory management across CPUs and GPUs. The portability across architectures with a single code implementation is achieved by automatically switching between diverse fine-grained parallelism backends (e.g., CUDA, HIP, OpenMP, pthreads, etc.) at compile time. The MATAR library solves many longstanding challenges associated with easily writing software that can run in parallel on any computer architecture. This work benefits projects seeking to write new C++ codes while also addressing the challenges of quickly making existing Fortran codes performant and portable over modern computer architectures with minimal syntactical changes from Fortran to C++. We demonstrate the feasibility of readily writing new C++ codes and modernizing existing codes with MATAR to be performant, parallel, and portable across diverse computer architectures.

Custom RISC-V architecture incorporating memristive in-memory computing

Due to the rise in data-intensive applications, the von Neumann bottleneck is increasingly restricting modern computer architectures, resulting to latency and energy consumption. Addressing this challenge necessitates a CMOS-compatible solution with high energy efficiency and significant parallelism. Utilizing resistive switching components within a 1T1R crossbar array and the application of Stanford RRAM model, this paper suggests an original method for in-memory computing. Moreover, this work shows a new way to advance the popular RISC-V architecture by including memristive crossbar array. It does this by adding a custom instruction set, special hardware blocks, and the Scouting Logic Scheme. These modifications serve both as a comprehensive testbed for the memory system and a proof of concept for the future integration of memristors in computing architectures. The proposed design undergoes extensive testing and power analysis to validate its functionality and performance under various conditions. The results demonstrate significant improvements in computational efficiency and energy savings, highlighting the potential of memristor-based in-memory computing systems to overcome current architectural limitations.

First-principles algorithms for ship motion simulation based on ARMA and trochoidal wave models

An approach for the direct simulation of ship behavior in heavy sea conditions using modern computers methods is described. The approach includes a model for wind-driven waves, algorithms for hydrodynamic pressure calculation, a solution of the diffraction problem, and the integration of the approach into a problem solution environment. An ARMA (autoregressive-moving average) model is used for the simulation of a hydrodynamically adequate spatial-temporal wave surface and integrated with a calculation of hydrodynamic pressure at any point under the wave surface. The integration of the wave pressure over the ship hull and the solution of the diffraction problem provides the excitation forces and moments and permits direct numerical simulation of ship motions in waves. An effective numerical implementation of the algorithms with mapping to modern computer architecture is described. The combination of the numerical algorithms with a visual simulation environment is presented as a virtual testbed.

A variational reformulation of molecular properties in electronic-structure theory.

Conventional quantum-mechanical calculations of molecular properties, such as dipole moments and electronic excitation energies, give errors that depend linearly on the error in the wave function. An exception is the electronic energy, whose error depends quadratically on the error in wave function. We here describe how all properties may be calculated with a quadratic error, by setting up a variational Lagrangian for the property of interest. Because the construction of the Lagrangian is less expensive than the calculation of the wave function, this approach substantially improves the accuracy of quantum-chemical calculations without increasing cost. As illustrated for excitation energies, this approach enables the accurate calculation of molecular properties for larger systems, with a short time-to-solution and in a manner well suited for modern computer architectures.

Automatic Parallelism Management

On any modern computer architecture today, parallelism comes with a modest cost, born from the creation and management of threads or tasks. Today, programmers battle this cost by manually optimizing/tuning their codes to minimize the cost of parallelism without harming its benefit, performance. This is a difficult battle: programmers must reason about architectural constant factors hidden behind layers of software abstractions, including thread schedulers and memory managers, and their impact on performance, also at scale. In languages that support higher-order functions, the battle hardens: higher order functions can make it difficult, if not impossible, to reason about the cost and benefits of parallelism. Motivated by these challenges and the numerous advantages of high-level languages, we believe that it has become essential to manage parallelism automatically so as to minimize its cost and maximize its benefit. This is a challenging problem, even when considered on a case-by-case, application-specific basis. But if a solution were possible, then it could combine the many correctness benefits of high-level languages with performance by managing parallelism without the programmer effort needed to ensure performance. This paper proposes techniques for such automatic management of parallelism by combining static (compilation) and run-time techniques. Specifically, we consider the Parallel ML language with task parallelism, and describe a compiler pipeline that embeds "potential parallelism" directly into the call-stack and avoids the cost of task creation by default. We then pair this compilation pipeline with a run-time system that dynamically converts potential parallelism into actual parallel tasks. Together, the compiler and run-time system guarantee that the cost of parallelism remains low without losing its benefit. We prove that our techniques have no asymptotic impact on the work and span of parallel programs and thus preserve their asymptotic properties. We implement the proposed techniques by extending the MPL compiler for Parallel ML and show that it can eliminate the burden of manual optimization while delivering good practical performance.

Polymer-Waveguide-Integrated 2D Semiconductor Heterostructures for Optical Communications.

The demand for high-speed and low-loss interconnects in modern computer architectures is difficult to satisfy by using traditional Si-based electronics. Although optical interconnects offer a promising solution owing to their high bandwidth, low energy dissipation, and high-speed processing, integrating elements such as a light source, detector, and modulator, comprising different materials with optical waveguides, presents many challenges in an integrated platform. Two-dimensional (2D) van der Waals (vdW) semiconductors have attracted considerable attention in vertically stackable optoelectronics and advanced flexible photonics. In this study, optoelectronic components for exciton-based photonic circuits are demonstrated by integrating lithographically patterned poly(methyl methacrylate) (PMMA) waveguides on 2D vdW devices. The excitonic signals generated from the 2D materials by using laser excitation were transmitted through patterned PMMA waveguides. By introducing an external electric field and combining vdW heterostructures, an excitonic switch, phototransistor, and guided-light photovoltaic device on SiO2/Si substrates were demonstrated.

Analisis Sistem Bus USB Dan PCI Pada Organisasi Arsitektur Komputer

Bus systems are an important component of modern computer organization and architecture. In this context, the two types of buses that stand out are Universal Serial Bus (USB) and Peripheral Component Interconnect (PCI). The USB bus is an interface standard commonly used to connect various external devices to a computer, while PCI is an internal bus that connects computer components. This study aims to analyze the role and characteristics of the USB and PCI bus systems in computer organization and architecture. The results of this analysis provide an in-depth understanding of the role of USB and PCI bus systems in modern computer organization and architecture. This information can help IT professionals and system designers make decisions regarding hardware connectivity and performance in a variety of computing environments.

ADAPTASI ORGANISASI TERHADAP PERKEMBANGAN ARSITEKTUR KOMPUTER MODERN

The rapid advancements in modern computer architecture pose significant challenges for organizations to remain relevant and efficient. This article explores the adaptation strategies implemented by organizations in response to the evolving landscape of contemporary computer architecture. The primary focus is on organizational efforts to align technological infrastructure, business processes, and organizational culture to support operational effectiveness. The discussion encompasses digital transformation, organizational cultural shifts, change management, cybersecurity, and the integration of new technologies as key elements in the adaptation strategy. By detailing the challenges and solutions applied, this research provides profound insights into how organizations can optimize their performance through intelligent adaptation to the developments in modern computer architecture. The findings of this study offer practical guidance for organizational leaders in designing successful adaptation strategies in this ever-changing era.

CUDA-BASED PARALLELIZATION OF GRADIENT BOOSTING AND BAGGING ALGORITHM FOR DIAGNOSING DIABETES

Data, its volume, structure, and form of presentation are among the most significant problems in working in the medical field. The probability of error is very high without innovative high-tech data analysis tools. It is easy to miss an important factor that is critical but lost among other, less important information. This work aims to study the proposed parallel gradient boosting algorithm in combination with the Bagging algorithm in the classification of diabetes to achieve greater stability and higher accuracy, reduce computational complexity and improve performance in medicine. The methods of parallelization of the Gradient Boosting algorithm in combination with the Bagging algorithm are investigated in the paper. Performance scores were obtained: approximately 7 using ThreadPoolExecutor and an eight-core computer system and 9.5 based on CUDA technology. Performance indicators that go to the unit are calculated. This, in turn, confirms the effectiveness of the proposed parallel algorithm. Another significant result of the study is improving algorithm accuracy by increasing the number of algorithms in the composition. The problem of diagnosing a patient's diabetes based on specific measurements included in the data set is considered. Detailed analysis and pre-processing of the selected dataset were performed. The parallelization of the proposed algorithm is implemented using the multi-core architecture of modern computers and CUDA technology. The process of learning models and training samples was parallelized. The theoretical estimation of the computational complexity of the offered parallel algorithm is given. A comparison of serial and parallel algorithm execution time using ThreadPoolExecutor when varying the number of threads and algorithms in the composition is presented. And also, the comparative analysis of time expenses at consecutive and parallel execution based on CPU and GPU is carried out.

On the use of a multigrid-reduction-in-time algorithm for multiscale convergence of turbulence simulations

Simulations of turbulent flow present challenges in terms of accuracy and affordability on modern highly-parallel computer architectures. A multigrid-reduction-in-time algorithm is used to provide a framework for separately evolving different scales of turbulence and for parallelizing the temporal domain, thereby increasing the concurrency. It is hypothesized that the space–time locality of the small scales of turbulence can be used to circumvent difficulties in applying temporal multigrid to flows dominated by inertial physics. For algorithms that fall well short of spectral accuracy (fourth-order is used in this work) attention must be paid to the accuracy of features on scales transferred between multigrid levels. Numerical experiments were performed using implicit large-eddy simulation. Results from applying the approach to an infinite-Reynolds number Taylor–Green flow and a double-shear flow at a Reynolds number of 11650 provide strong evidence that the approach has merit. The multigrid-reduction-in-time framework can be used to parallelize the temporal domain of a high-Reynolds-number turbulent flow and permit independent convergence of different scales. Establishing this foundation allows for future research in reducing the wall-clock time to solve turbulent flows while retaining the same accuracy as sequential solvers. Current performance results from parallelizing the temporal domain are not competitive with those from sequential-in-time methods.

A method of defense against cache timing attack in non-volatile memory

Attackers of modern computer architecture found that cache access latency difference between cache hit and cache miss is a point where secure data are overlooked. To prevent such data leakage, cache partitioning technique is utilized for defenders via cache hit isolation. Although this approach is effective in increasing resistance against cache timing attack, it is not suitable for emerging memory system, which is based on non-volatile memories, because it overlooks the weaknesses of the write operations. This paper proposes a secure-aware partitioning guide architecture to improve performance and write endurance by removing the necessity of cache flushing. During changing cache partitioning status, the write counts are considered for the new status and no cache lines are evicted in the proposal. As a result, the lifetime is extended by 1.77 times and the penalty of cache flushing is saved by 7.8%.

Deep Learning for Edge Computing Applications: A Comprehensive Survey

Edge computing is a modern computer architecture that processes data quickly and efficiently close to its point of origin, hence avoiding slowdowns caused by network latency and capacity limitations. By moving processing power to the network’s perimeter, edge computing decreases the load on central data centers and reduces the time it takes for users to submit data. Therefore, access latency may become a barrier, potentially negating the benefits of edge computing, particularly for applications that need a great deal of data.. Edge computing has some challenges, such as security, incomplete data, investment costs, and maintenance costs. In this research, we undertake a thorough analysis of edge computing, how edge device placement improves performance in IoT networks, compare various edge computing implementations, and explain various difficulties encountered during edge computing implementation. This study aims to promote creative edge-based Internet of Things security design by thoroughly examining existing Internet of Things security solutions at the edge layer and facilitate the dynamic deployment of edge devices.

Computationally Efficient Cellular Automata‐Based Full‐Field Models of Static Recrystallization: A Perspective Review

The evolution of metallic material microstructures under thermomechanical treatment is a critical element that influences the in‐use properties of the final product. In the last four decades, many researchers around the world focused on reliable numerical recreation of phenomena that occur during metal processing. Particular attention is put on the phase transformation, texture evolution, and recrystallization predictions to simulate material behavior at the subsequent processing stages. In recent years, approaches taking into account explicit representation of morphological elements during simulation are becoming more frequently used even at the industrial scale. One of those methods addressed within the current article in application to static recrystallization (SRX) modeling is the cellular automata (CA) approach. A review of the CA‐based full‐field SRX models highlights the progress in capabilities of developed approaches in consideration of various mechanisms controlling microstructure evolution like heterogeneous energy distribution, probabilistic or physics‐based nucleation, grain growth driven by different driving forces, or grain boundary migration is presented within the article. The issue of the computational time associated with 3D CA modeling is particularly addressed. Possible approaches to reducing simulation times based on efficient use of modern computer architecture are finally evaluated as guidelines for further model development.

Fundamentals of Fast Tsunami Wave Parameter Determination Technology for Hazard Mitigation.

This paper describes two basic elements of the smart technology, allowing us to bring to a new level the problem of early warning and mitigation of tsunami hazards for the so-called near zone events (when a destructive tsunami wave reaches the nearest coast in tens of minutes after the earthquake). The sensors system, installed in a reasonable way (to detect a wave as early as possible), is capable of transmitting the necessary raw data (measured wave profile) in a real time mode to a processing center. The smart (based on mathematical theory) algorithm can reconstruct an actual source shape within a few seconds using just a part of the measured wave record. Using modern computer architectures (Graphic Processing Units or Field Programmable Gates Array) allows computing tsunami wave propagation from the source to shoreline in 1–2 min, which is comparable to the performance of a supercomputer. As is observed, the inundation zone could be evaluated reasonably correctly as the coastal area below two thirds of the tsunami wave height at a particular location. In total, the achieved performance of the two above mentioned algorithms makes it possible to evaluate timely the tsunami wave heights along the coastline to approximate the expected inundation zone, and therefore, to suggest (in case of necessity) evacuation measures to save lives.

Decimal Versus Binary Representation of Numbers in Computers

The dichotomy created by the advent of computers and brought up by the title of this column was a major quandary in the early days of the computer revolution, causing major controversy in both the academic and commercial communities involved in the development of modern computer architectures. Even though the controversy was eventually decided (in favor of binary representation; all commercially available computers use a binary internal architecture), echoes of that controversy still affect computer usage today by creating errors when data is transferred between computers, especially in the chemometric world. A close examination of the consequences reveals a previously unexpected error source.

Combining p-multigrid and Multigrid Reduction in Time methods to obtain a scalable solver for Isogeometric Analysis

The use of sequential time integration schemes becomes more and more the bottleneck within large-scale computations due to a stagnation of processor’s clock speeds. In this study, we combine the parallel-in-time Multigrid Reduction in Time method with a p-multigrid method to obtain a scalable solver specifically designed for Isogeometric Analysis. Numerical results obtained for two- and three-dimensional benchmark problems show the overall scalability of the proposed method on modern computer architectures and a significant improvement in terms of CPU timings compared to the use of standard spatial solvers.

Classifying Co-resident Computer Programs Using Information Revealed by Resource Contention

Modern computer architectures are complex, containing numerous components that can unintentionally reveal system operating properties. Defensive security professionals seek to minimize this kind of exposure while adversaries can leverage the data to attain an advantage. This article presents a novel covert interrogator program technique using light-weight sensor programs to target integer, floating point, and memory units within a computer’s architecture to collect data that can be used to match a running program to a known set of programs with up to 100% accuracy under simultaneous multithreading conditions. This technique is applicable to a broad spectrum of architectural components, does not rely on specific vulnerabilities, nor requires elevated privileges. Furthermore, this research demonstrates the technique in a system with operating system containers intended to provide isolation guarantees that limit a user’s ability to observe the activity of other users. In essence, this research exploits observable noise that is present whenever a program executes on a modern computer. This article presents interrogator program design considerations, a machine learning approach to identify models with high classification accuracy, and measures the effectiveness of the approach under a variety of program execution scenarios.

Sequential Monte-Carlo algorithms for Bayesian model calibration – A review and method comparison✰

Bayesian inference has become an important framework for calibrating complex ecological and environmental models. Markov-Chain Monte Carlo (MCMC) algorithms are the methodological backbone of this framework, but they are not easily parallelizable and can thus not make optimal use of modern computer architectures. A possible solution is the use of Sequential Monte Carlo (SMC) algorithms. Currently, SMCs are used mainly for Bayesian state updating, for example in weather forecasting, and are thought to be less efficient for parameter calibration than MCMCs. Unlike MCMCs, however, SMCs are easily parallelizable. Thus, SMCs may become an interesting alternative when modelers have access to parallel computing environments. The purpose of this paper is to provide an introduction to SMC algorithms for Bayesian model calibration, and to explore the trade-off between efficiency and parallelizability for MCMC and SMC algorithms. To that end, we discuss different SMC variants, and benchmark them against a state-of-the-art MCMC algorithm by calibrating three ecological models of increasing complexity. Our results show that, with appropriately chosen settings, SMCs can be faster than state-of-the-art MCMC algorithms when a sufficiently large number of parallel cores are available and when the model runtime is large compared to communication overhead for parallelization (on our hardware, a model runtime of 20 ms was enough to favor SMC algorithms). Efficient SMC settings were characterized by a balanced mix of SMC filtering and MCMC mutation steps, suggesting that mixing MCMC and SMC principles may be ideal for creating efficient and parallelizable calibration algorithms. The algorithms used in this study are provided within the BayesianTools R package for Bayesian inference with complex ecological models.

Sharing non‐cache‐coherent memory with bounded incoherence

SummaryCache coherence in modern computer architectures enables easier programming by sharing data across multiple processors. Unfortunately, it can also limit scalability due to cache coherency traffic initiated by competing memory accesses. Rack‐scale systems introduce shared memory across a whole rack, but without inter‐node cache coherence. This poses memory management and concurrency control challenges for applications that must explicitly manage cache‐lines. To fully utilize rack‐scale systems for low‐latency and scalable computation, applications need to maintain cached memory accesses in spite of non‐coherency. This paper introduces Bounded Incoherence, a memory consistency model that enables cached access to shared data‐structures in non‐cache‐coherency memory. It ensures that updates to memory on one node are visible within at most a bounded amount of time on all other nodes. We evaluate this memory model on modified PowerGraph graph processing framework, and boost its performance by 30% with eight sockets by enabling cached‐access to data‐structures.

Parallelization of Finding the Current Coordinates of the Lidar Based on the Genetic Algorithm and OpenMP Technology

The problem of determining the position of the lidar with optimal accuracy is relevant in various fields of application. This is an important task of robotics that is widely used as a model when planning the route of vehicles, flight control systems, navigation systems, machine learning, and managing economic efficiency, a study of land degradation processes, planning and control of agricultural production stages, land inventory to evaluations of the consequences of various environmental impacts. The paper provides a detailed analysis of the proposed parallelization algorithm for solving the problem of determining the current position of the lidar. To optimize the computing process in order to accelerate and have the possibility of obtaining a real-time result, the OpenMP parallel computing technology is used. It is also possible to significantly reduce the computational complexity of the successive variant. A number of numerical experiments on the multi-core architecture of modern computers have been carried out. As a result, it was possible to accelerate the computing process about eight times and achieve an efficiency of 0.97. It is shown that a special difference in time of execution of a sequential and parallel algorithm manages to increase the number of measurements of lidar and iterations, which is relevant in simulating various problems of robotics. The obtained results can be substantially improved by selecting a computing system where the number of cores is more than eight. The main areas of application of the developed method are described, its shortcomings and prospects for further research are provided.