FPGA Design Research Articles

MKIDGen3: Energy-resolving, single-photon-counting microwave kinetic inductance detector readout on a radio frequency system-on-chip.

Microwave Kinetic Inductance Detectors (MKIDs) are superconducting detectors capable of single-photon counting with energy resolution across the ultraviolet, optical, and infrared (UVOIR) spectrum with microsecond timing precision. MKIDs are also multiplexable, providing a feasible way to create large-format, cryogenic arrays for sensitive imaging applications in biology, astronomy, and quantum information. Building large, cryogenic MKID arrays requires processing highly multiplexed, wideband readout signals in real time; this task has previously required large, heavy, and power-intensive custom electronics. In this work, we present the third-generation UVOIR MKID readout system (Gen3), which is capable of reading out twice as many detectors with an order of magnitude lower power, weight, volume, and cost-per-pixel as compared to the previous system. Gen3 leverages the Xilinx RFSoC4x2 platform to read out 2048, 1MHz MKID channels per board. The system takes a modern approach to FPGA design using Vitis High-Level Synthesis to specify signal processing blocks in C/C++, Vivado ML intelligent design runs to inform implementation strategy and close timing, and Python productivity for Zynq to simplify interacting with and programming the FPGA using Python. This design suite and tool flow allows general users to contribute to and maintain the design and positions Gen3 to rapidly migrate to future platforms as they become available. In this work, we describe the system requirements, design, and implementation. We also provide performance characterization details and show that the system achieves detector-limited resolving power in the case of few readout tones and minimal degradation with all 2048 tones. Planned upgrades and future work are also discussed. The Gen3 MKID readout system is fully open-source and is expected to facilitate future array scaling to megapixel-sized formats and increase the feasibility of deploying UVOIR MKIDs in space.

A Field-Programmable Gate Array-Based Quasi-Cyclic Low-Density Parity-Check Decoder with High Throughput and Excellent Decoding Performance for 5G New-Radio Standards

This work presents a novel fully parallel decoder architecture designed for high-throughput decoding of Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes within the context of 5G New-Radio (NR) communication. The design uses the layered Min-Sum (MS) algorithm and focuses on increasing throughput to meet the strict needs of enhanced Mobile BroadBand (eMBB) applications. We incorporated a Sub-Optimal Low-Latency (SOLL) technique to enhance the critical check node processing stage inherent to the MS algorithm. This technique efficiently computes the two minimum values, rendering the architecture well-suited for specific Ultra-Reliable Low-Latency Communication (URLLC) scenarios. We design the decoder to be reconfigurable, enabling efficient operation across all expansion factors. We rigorously validate the decoder’s effectiveness through meticulous bit-error-rate (BER) performance evaluations using Hardware Description Language (HDL) co-simulation. This co-simulation utilizes a well-established suite of tools encompassing MATLAB/Simulink for system modeling and Vivado, a prominent FPGA design suite, for hardware representation. With 380,737 Look-Up Tables (LUTs) and 32,898 registers, the decoder’s implementation on a Virtex-7 XC7VX980T FPGA platform by AMD/Xilinx shows good hardware utilization. The architecture attains a robust operating frequency of 304.5 MHz and a normalized throughput of 49.5 Gbps, marking a 36% enhancement compared to the state-of-the-art. This advancement propels decoding capabilities to meet the demands of high-speed data processing.

Predicting routability of FPGA design by learning complex network images

Accurately and efficiently predicting the routability of modern FPGAs in the early stages is significant for achieving ultimate optimization. We propose a novel approach for FPGA routability prediction by the CBAM-CNN model incorporating an attention mechanism to learn complex network images. For an FPGA placement design, we innovatively extract the circuit-related and complex network-related features associated with routing congestion and map them into a complex network image. The approach demonstrates a remarkable performance in routability prediction, surpassing the recent machine learning models in accuracy, precision, sensitivity, and specificity. Notably, the Matthews correlation coefficient has improved by 6.15% compared with the state-of-the-art convolutional neural network model (Alhyari et al., 2019). The additional ROC (Receiver Operating Characteristic Curve) analysis highlights the model’s classification efficiency. We estimate the significance of complex network features in predicting FPGA design routability, presenting in descending order of Degree, Strength, Eigenvector, and Betweenness.

On-orbit update and scrubbing design of SRAM FPGA for spacecraft

Abstract In the design of spacecraft products, improving the anti-irradiation ability of products, especially the anti-single Event Upsets ability of electronic products, is an important research area to improve the reliability of products. As a programmable device, FPGA is widely used in electronic products. In this paper, the reliability improvement method of Xilinx Company’s SRAM FPGA is studied, and a scheme for on-orbit update and scrubbing refresh of SRAM FPGA is designed using anti-fuse FPGA. This scheme can support on-orbit updates and scrubbing of multiple SRAM FPGAs at the same time, which can meet specific engineering applications. Through simulation verification and actual measurement verification, it can effectively improve the ability of spacecraft on-orbit fault handling and function upgrading. It provides a way to improve the reliability of electronic products.

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

In recent years, the adoption of FPGAs in datacenters has increased, with a growing number of users choosing High-Level Synthesis (HLS) as their preferred programming method. While HLS simplifies FPGA programming, one notable challenge arises when scaling up designs for modern datacenter FPGAs that comprise multiple dies. The extra delays introduced due to die crossings and routing congestion can significantly degrade the frequency of large designs on these FPGA boards. Due to the gap between HLS design and physical design, it is challenging for HLS programmers to analyze and identify the root causes, and fix their HLS design to achieve better timing closure. Recent efforts have aimed to address these issues by employing coarse-grained floorplanning and pipelining strategies on task-parallel HLS designs where multiple tasks run concurrently and communicate through FIFO stream channels. However, many applications are not streaming friendly and many existing accelerator designs heavily rely on buffer channel based communication between tasks. In this work, we take a step further to support a task-parallel programming model where tasks can communicate via both FIFO stream channels and buffer channels. To achieve this goal, we design and implement the PASTA framework, which takes a large task-parallel HLS design as input and automatically generates a high-frequency FPGA accelerator via HLS and physical design co-optimization. Our framework introduces a latency-insensitive buffer channel design, which supports memory partitioning and ping-pong buffering while remaining compatible with vendor HLS tools. On the frontend, we provide an easy-to-use programming model for utilizing the proposed buffer channel; while on the backend, we implement efficient placement and pipelining strategies for the proposed buffer channel. To validate the effectiveness of our framework, we test it on four widely used Rodinia HLS benchmarks and two real-world accelerator designs and show an average frequency improvement of 25%, with peak improvements of up to 89% on AMD/Xilinx Alveo U280 boards compared to Vitis HLS baselines.

Sorting Algorithms Comparison on FPGA and Intel i7 Architectures

Sorting Algorithms Comparison on FPGA and Intel i7 Architectures

A Computation of the Ninth Dedekind Number Using FPGA Supercomputing

This manuscript makes the claim of having computed the \(9\) th Dedekind number, D(9). This was done by accelerating the core operation of the process with an efficient FPGA design that outperforms an optimized 64-core CPU reference by 95 \(\times\) . The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn University. The resulting value for D(9) is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490 M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. The paper explains the mathematical approach in the first part, before putting the focus on a deep dive into the FPGA accelerator implementation followed by a performance analysis. The FPGA implementation was done in Register-Transfer Level using a dual-clock architecture and shows how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800 FPGAs. The total compute time used was 47,000 FPGA hours.

CSAIL2019 Crypto-Puzzle Solver Architecture

tThe CSAIL2019 time-lock puzzle is an unsolved cryptographic challenge introduced by Ron Rivest in 2019, replacing the solved LCS35 puzzle. Solving these types of puzzles requires large amounts of intrinsically sequential computations, with each iteration performing a very large (3,072-bit for CSAIL2019) modular multiplication operation. The complexity of each iteration is several times greater than known field-programmable gate array (FPGA) implementations, and the number of iterations has been increased by about 1,000x compared with LCS35. Because of the high complexity of this new puzzle, a number of intermediate, or milestone, versions of the puzzle have been specified. In this article, we present several FPGA architectures for the CSAIL2019 solver, which we implement on a medium-sized Intel Agilex device. We develop a new multi-cycle modular multiplication method, which is flexible and can fit on a wide variety of sizes of current FPGAs. We introduce a class of multi-cycle squarer-based architectures that allow for better resource and area trade-offs. We also demonstrate a new approach for improving the fitting and timing closure of large, chip-filling arithmetic designs. We used the solver to compute the first 23 out of 28 milestone solutions of the puzzle, which are the first reported results for this problem.

Multiple-base Logarithmic Quantization and Application in Reduced Precision AI Computations

The power of logarithmic quantizations and computations has been recognized as a useful tool in optimizing the performance of large ML models. There are plenty of applications of ML techniques in digital preservation. The accuracy of computations may play a crucial role in the corresponding algorithms. In this article, we provide results that demonstrate significantly better quantization signal-to-noise ratio performance thanks to multiple-base logarithmic number systems (MDLNS) in comparison with the floating point quantizations that use the same number of bits. On a hardware level, we present details about our Xilinx VCU-128 FPGA design for dot product and matrix vector computations. The MDLNS matrix-vector design significantly outperforms equivalent fixed-point binary designs in terms of area (A) and time (T) complexity and power consumption as evidenced by a 4 × scaling of AT 2 metric for VLSI performance, and 57% increase in computational throughput per watt compared to fixed-point arithmetic.

A real-time cardiac output monitoring system based on photoplethysmography

Abstract Cardiac output is a critical parameter for assessing the cardiovascular system, and thermodilution is commonly used as CO monitoring in clinical settings. Thermodilution cannot be applied in continuous monitoring due to invasion. Photoplethysmography signal originates from the cardiovascular system. We proposed a CO continuous monitoring system based on photoplethysmography and deep learning method. PPG waveform parameters are extracted during the pre-processing stage, and fed into the deep learning model to calculate cardiac output. The system employs an analog front-end chip and an HPS_FPGA architecture to capture PPG signals. The pre-processing and the deep learning model-driven algorithm are designed in Python on the custom Linux for HPS. It realizes the real-time processing of the PPG signals and the continuous monitoring of cardiac output. Validated by an FPGA, the system reported average cardiac output monitoring results of approximately 5.09 L/min at rest and about 7.39 L/min after exercise.

Design of a High-Precision Self-Balancing Potential Transformer Calibrator

Potential transformers are vital for measuring and protecting the power grid. Their accuracy and reliability directly impact the stability and security of the power system. To address the issues with traditional high-precision potential transformer calibrators, such as cumbersome operation and low efficiency, a high-precision potential transformer calibrator has been developed. The calibrator is based on an embedded system architecture of FPGA and ARM. It uses a high-precision current comparator along with feedback control technology. By monitoring and adjusting the error feedback voltage, it can perform the automated calibration of potential transformers with an accuracy class of 0.0001. The measurement ranges from 0.00001% to 200.0%. This study can be adapted to meet the development needs of modern digital measurement systems.

RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost

Over the last decade, there has been a rise in cyberattacks, particularly ransomware, causing significant disruption and financial repercussions across public and private sectors. Tremendous efforts have been spent on developing techniques to detect ransomware to, ideally, protect data or have as minimum data loss as possible. Ransomware attacks are becoming more frequent and sophisticated as there is a constant tussle between attackers and cybersecurity defenders. Machine Learning (ML) approaches have proven more effective in detecting ransomware than classical signature-based detection. In particular, tree-based algorithms such as Decision Trees (DT), Random Forest (RF), and eXtreme Gradient Boosting (XGBoost) spike up interest among cybersecurity researchers. However, due to the nature of the problem, traditional CPUs and GPUs fail to keep up with the desired performance, especially for large data workloads. Thus, the problem demands a customized solution to detect the ransomware. Here, we propose an FPGA accelerated tree-based ML model for multi-dataset ransomware detection. We show the capability of the proposed prototype to address the problem from more than one set of features, reducing false positive and negative rates to have robust predictions by looking at Hardware Performance Counters (HPCs), Operating System (OS) calls, and network traffic information simultaneously. With 1000 samples per batch, the FPGA prototype has 65.8x and 4.1x lower latency over the CPU and GPU, respectively. Moreover, the FPGA design is up to 11.3x cost-effective and 643x energy-efficient compared to the CPU and 3x cost-effective and 16.8x energy-efficient over the GPU.

Design and FPGA Implementation of Signal Strength Measurement Techniques for Satellite Communication Systems

Communication receivers perform three major functions, frequency down conversion, IF demodulation and subcarrier demodulation. The functioning of a receiver is mainly controlled by input signal strength and relative dynamics. Signal strength is measured in terms of Signal to Noise ratio (SNR) and Carrier to Noise power density (C/No). Any measure of signal strength indirectly gives information about receiver performance for that period. Apart from this, SNR measurement in close loop with Phase Locked Loop (PLL) parameter forms the adaptive PLL system, which is one of the driving forces for this paper. The focus of this paper is to find suitable signal strength measurement techniques and their implementation for satellite communication systems. Signal to Noise Variance method (SNV) and Narrow band Wide band Power Ratio (NWPR) methods are considered based on the performance and realization aspects. All techniques require division, logarithm, and multiplication functions for their realization in hardware. CO-ordinate Rotation Digital Computer (CORDIC) algorithm is considered for realizing logarithm function. A comparison study is done for developed algorithm with Intellectual Property (IP) core. Developed SNR techniques are simulated for Binary Phase Shift Keying (BPSK) demodulator system and performance is evaluated for Additive White Gaussian Noise (AWGN). The paper describes the FPGA design and simulations of these techniques. Developed design is targeted to commercial and space qualified FPGA platforms. FPGA implementations results are compared with system level simulation results, and both are found to be satisfactory. Application of developed system in adaptive BPSK demodulator is also presented.

A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation

Since multiplication is a complex and resource-consuming operation, it is very effective on the speed performance of a processor. In this regard, fast multiplication unit design is important in digital system architectures. FPGA hardware, which is efficient for the implementation and rapid prototyping of today’s digital system architectures, is becoming widespread. Therefore, in this study it aimed to design a fast radix-16 Booth multiplier based on the FPGA architecture. Booth multiplier implementation is preferred because it is relatively simple and efficient. The sizes of the multiplexers, which have an impact on the operating period in the encoder part of the proposed multiplier, reduced in the designed architecture by using a simple algorithm. To increase the speed performance of the system, the pipeline technique is used and parallelization is preferred in the tree structure in addition of the partial products. The effects of different multiplexer sizes, bit lengths and pipeline stages on the operating period of the system and other performance metrics examined. Different designs and the results obtained presented. According to the results, the multiplier hardware architectures designed in this study exhibit effective results in terms of speed performance.

Implementation of Dimension Order Routing Algorithm on Reconfigurable Hardware for NoC applications

Inter-processing element communication encounters significant hurdles arising from constraints in power consumption, physical space, and data transfer speed. Storing data packets temporarily during communication uses a lot of the chip's power. Many contemporary network-on-chip (NoC) architectures are heavily resource-intensive due to the extensive use of router buffers. Eliminating these buffers and virtual channels can streamline router design and reduce power consumption. The routing and arbitration strategies implemented within a NoC router are pivotal for optimizing the overall performance of the NoC mesh. The routing algorithm plays a critical role in NoC systems, as it is responsible for balancing traffic load across network channels, even in scenarios of asymmetric traffic distribution. This paper introduces a model for X-Y routing algorithms, specifically tailored for implementation on FPGA platforms utilizing a flexible state diagram. The distinctive contribution of this research lies in its synthesis and optimized realization of the X-Y routing algorithm on FPGAs, providing Network-on-Chip (NoC) designers with a robust framework for developing efficient routers tailored to their FPGA architectures.

FPGA-based control system for real-time driving of UHD Micro-LED display with color calibration

Micro-LED technology offers numerous advantages, including high brightness, low power consumption, and superior color performance. However, driving micro LED displays requires complex control algorithms and high-speed data processing. To address these challenges, this paper presents the development of a real-time FPGA-based control system for a 68-inch 4K/60Hz micro-LED display. The objective of this project was to create a high-performance control system capable of driving the micro-LED display with precise color accuracy, supporting 10-bit color depth for enhanced color rendition. One crucial aspect of the system is color calibration, which ensures accurate color reproduction across the display, maintaining consistent and vibrant colors. By incorporating advanced color calibration techniques, the system achieves excellent color consistency and fidelity, providing a visually stunning viewing experience. Moreover, the system incorporates hot plug functionality, allowing for seamless reconnection of the display after Ethernet disconnection. This feature ensures uninterrupted operation and enhances user experience. In FPGA design, the proposed system demonstrates the feasibility and effectiveness of real-time control in driving micro-LED displays, offering improved color performance and reliable operation in various applications.

FPGA implementation of IIR elliptic filters for de-noising ECG signal

De-noising of ECG signal is very much necessary to monitor the heart health and to diagnose disease. This paper presents a real time de-noising system that efficiently wiped out the noises from corrupted ECG signal and improves its SNR which enhances the interpretation of features present in ECG signal. This proposed system is designed with three Infinite Impulse Response (IIR) elliptic filters in cascaded direct form II structure and is implemented on the FPGA platform. Total 376 ECG samples are taken from the open access public database physiobank. All the architectural level FPGA designs have been developed in Xilinx System Generator (XSG) and implemented on Xilinx Zynq 7000 board. Our design utilized only 3.87 % of the total available resource and consumed 0.321 watt on-chip power. Worst Negative Slack (WNS) for the critical path is 2.101 ns. The positive value of WNS signifies our hardware design implementation run successfully by meeting the required time constraint. To judge the performance of the proposed design, the measurement matrices SNR Improvement, RMSE, PRD, SSNR and SINAD are calculated and achieved 81.11% , 88.89% and 85.41% accuracy for ECG recordings of ECG-ID, MIT-BIH Normal Sinus Rhythm and MIT-BIH Arrhythmia database respectively. The novelty of this proposed denoising system is its robustness, which work satisfactorily for Baseline Wander (BW), Electrode Motion (EM), Power Line Interference (PLI), Muscle or Electromyography (EMG) and as well as Additive White Gaussian Noise (AWGN).

AES 128 Bit Optimization: High-Speed and Area-Efficient through Loop Unrolling

This study introduces a high-throughput FPGA implementation of AES-128, prioritizing efficiency for robust security and fast data processing needs. AES-128 is renowned for its security and widespread use in various applications. Employing techniques like loop unrolling and pipelining, the implementation maximizes throughput and customizes AES for FPGA architectures. A novel optimization approach, "new-affine-transformation," reduces resource demands and latency for the Sub-Bytes function. The AES architecture is strategically modified for efficiency, with rearranged functions and streamlined processing. The implementation, in VHDL and utilizing Xilinx Virtex-5 FPGA, achieves remarkable performance: 37.9 Gbps (encryption) and 38.5 Gbps (decryption) throughput at frequencies of 296.789 MHz (encryption) and 300.806 MHz (decryption). Resource utilization is efficient, with 264 (encryption) and 260 (decryption) slice registers and 1044 (encryption) and 1581 (decryption) total slices. Keywords: AES, FPGA, cryptography, encryption, decryption, throughput, plain text, cipher text

FPGA-base object tracking: integrating deep learning and sensor fusion with Kalman filter

This research presents an integrated approach for object detection and tracking in autonomous perception systems, combining deep learning techniques for object detection with sensor fusion and field programmable gate array (FPGA-based) hardware implementation of the Kalman filter. This approach is suitable for applications like autonomous vehicles, robotics, and augmented reality. The study explores the seamless integration of pre-trained deep learning models, sensor data from a depth camera, real-sense D435, and FPGA-based Kalman filtering to achieve robust and accurate 3D position and 2D size estimation of tracked objects while maintaining low latency. The object detection and feature extraction are implemented on a central processing unit (CPU), and the Kalman filter sensor fusion with universal asynchronous receiver transmitter (UART) communication is implemented on a Basys 3 FPGA board that performs 8 times faster compared to the software approach. The experimental result provides the hardware resource utilization of about 29% of look-up tables, 6% of lookup table RAMs (LUTRAM), 15% of Flip-flops, 32% of Block-RAM, 38% of DSP blocks operating at 100 MHz, and 230400 baud rates for the UART. The whole FPGA design executes at 2.1 milliseconds, the Kalman filter executes at 240 microseconds, and the UART at 1.86 milliseconds.

NV color center fluorescence signal measurement based on FPGA architecture

Nitrogen-vacancy (NV) quantum defects in diamond are sensitive detectors of magnetic fields. Then, the existing sensing technologies based on diamond NV centers rely on bulky and expensive instruments, which must be replaced by a more compact design. Here we combine NV quantum sensing technology with integrated circuit technology to create a compact and easy-to-operate platform. Using the existing integrated circuit technology, we integrate the lock-in amplifier, microwave generator and TTL modulator together. with this platform, we can obtain a magnetic sensitivity of 5.72μT/Hz 1/2.