Switching System Architecture Research Articles

비행제어법칙 전환시스템 개발

본 논문은 비행 중 비행제어법칙을 전환함으로써 실험 대상 비행제어법칙을 검증할 수 있는 비행제어법칙 전환시스템 개발에 관한 논문이다. 본 연구를 통하여 제어법칙 간 전환에 따른 천이응답을 최소화하기 위한 페이더 설계 및 대기 모드 상태에 있는 비행제어법칙의 적분기 안정화 설계가 도입되었다. 두 개의 제어법칙 간 데이터 통신은 1553 통신 방식을 채택하였다. 본 논문은 개발된 비행제어법칙 전환시스템의 구조 및 주요 개념 설계 연구 및 고등훈련기급의 비행성 평가 시뮬레이터를 이용한 시스템 검증 결과를 포함한다. This paper deals with a development of flight control law switching system which can be used for flight test of the research control law by switching control law during flight. Through this research program, fader logic and integrator stabilization design has been introduced to minimize the transient response of aircraft caused by flight control law switching and to prevent the divergence of the integrator included in the control law in standby mode. MIL-STD-1553B communication was applied to transfer the data between the two control laws. This paper introduce the control law switching system architecture and major design concept and include the system verification and validation result performed on the flying quality simulator of the advanced trainer.

Three-dimensional micro-optical switching system architecture using slab-waveguide-based micro-optical switches

A high-speed, large-scale architecture, three-dimensional micro-optical switching system (3-D MOSS) is proposed. A switching network is divided into subnetwork blocks, followed by stacking them to construct a multilayer structure. The interblock waveguide connection is replaced with short-distance vertical optical wiring, that is, optical z connections. Thus, 3D-MOSS, in contrast with conventional planar structures, reduces waveguide cross points, wiring length, and system size. Expected applications are switching for fiber communications, reconfigurable 3-D micro optoelectronic (OE) systems, and so on. 3D-MOSS consists of OE films, in which thin-film high-speed micro-optical switches are embedded. Two critical issues for 3D-MOSS, micro-optical switch and optical z connection, are investigated. The beam propagation method (BPM) calculation shows that waveguide-prism-deflector micro-optical switch (WPD-MOS), in which prism-shaped electrodes are formed on an electro-optic slab waveguide, is suitable for the micro-optical switch. The finite difference time domain method (FDTD)/BPM coupled simulation demonstrates a possibility of low-loss optical z connection in a 4-μm width waveguide-based 3-D micro-optical network. Performance of 3D-MOSS for a 32×32 Banyan network is assessed as follows: system size is 2250 (length)×600 (width)×320 (height) μm 3 , operation voltage 110 V, switching speed 5 /s, and maximum insertion loss 14 dB. This indicates the viability of 3D-MOSS from viewpoints of channel count, switching speed, thermal management, and power budget. A material/cost-saving device integration process photolithographic packaging with selectively occupied repeated transfer (PL-Pack with SORT) is briefly described as an example of a fabrication method for 3D-MOSS.

Breakthrough technologies for the high-performance electrical ATM switching system

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The first step system was to use advanced Si-bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 /spl mu/m bipolar SST technologies and Cu-polyimide multilayer MCM realized a 160 Gb/s throughput ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper first reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8/spl times/8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems.

TORUS: terabit-per-second ATM switching system architecture based on distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4/spl times/2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch.

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 /spl mu/m E/D MESFET process.

Distributed Switching Architecture Trends and Concepts

The increasing sophistication of the global telecommunications business is creating new, more demanding requirements for switching systems. To meet these requirements, AT&T must introduce the most up-to-date technologies for advanced capabilities, such as high-bandwidth services, Personal Communication Services (PCS), and increased network intelligence in a timely, cost-effective manner. Switching systems that are adaptable, evolvable, and able to gracefully incorporate these new capabilities and technologies are in the best position to meet market needs. Such switching systems have architectures that are both evolvable — able to incorporate new technology and new development processes within their overall structure — and maintainable — able to accommodate new features continually without rapid increases in the cost of development or equipment. This paper examines the choices for a switching system architecture by defining the functional components of a switch and examining the choices for implementing them.

A hyperdistributed switching system architecture for B-ISDN

The broadband integrated services digital network (B-ISDN) is expected to realize a high-speed network. Information with diversified classes of quality must be transmitted on the network, from the 64-kbit/s voice signal to the several tens Mbit/s video signal. Another aspect is that the voice and the video signals are sensitive to the delay, and severe requirements are imposed on the data error. For the switching system in B-ISDN, an architecture is required which fully utilizes the advantages of the asynchronous transfer mode (ATM) communication system, where the effective use of the network is considered by multiplexing the multimedia. This paper proposes the hyperdistributed architecture to be applied to such a broadband communication environment. In the proposed system, front-end processing modules (FPM), which are independent ATM nodes with the call processing functions, are placed according to the scale of system. The central switching module (CSM) with the single-stage distributed ATM switch to connect FPM is provided only with the self-routing function based on the routing information in the ATM cell header. For the proposed hyperdistributed architecture, the design for the communication channel based on the ATM nonblocking condition, as well as the transfer route determination, are discussed. Then the allocation of the quality class control using the shared buffer ATM switch is discussed which can construct an efficient network satisfying the diversified quality requirements.

A large scale ATM switching system architecture for multimedia communications

A large scale ATM switching system architecture for multimedia communications

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers. >

Terabit-per second throughput switches for broadband central offices: an overview

The design of a broadband central office (CO) switch based on the SONET standard and the asynchronous transfer mode (ATM) protocol is addressed. An overview is given of the next generation switch (NGS), which has been proposed as a functional architecture for broadband networks and switching systems. The NGS consists of a number of different functional modules (interface, control, operations, service, and fabric), interconnected by open interfaces, that together form a high-speed large-throughput switching system. The interface modules and fabric modules, which embody some of the more difficult technological problems encountered in realizing terabit-per-second switches, are examined in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High‐speed broadband circuit switching system architecture

AbstractThis paper considers the speed of communication where NTSC and HDTV video signal is encoded into digital forms, and proposes a high‐speed broadband circuit switching system which realizes the integrated services covering communication services and distribution services. The former include the end‐to‐end communication such as TV conference and the video retrieval such as image inquiry system, and the latter includes the CATV.The proposed method has the following features: (1) The communication services and the distribution services are distinguished by using layer 3 of I interface protocol. The video channel selected by the subscriber is transferred between the subscriber and the service processing node of the video distribution system, using the high‐level layer signal; (2) considering the uncertain demand, a building block structure is adopted, where the unit is the small‐scale independent switching and distribution module with several tens to several hundreds of subscribers; (3) the load‐function distributed control scheme is adopted.In the communication services, the functions are divided into the modules of subscriber accommodation, intermodule connection, inter‐office signal processing and system management. In the distribution services, the divided modules such as the selection of video channel and the interface processing to the video operation center are executed in the almost complete processing within the module, which helps to reduce the communication traffic between modules.

InP-based optical switch module operating through carrier-induced refractive index change

Study of an lnP-based optical switch operating through carrierinduced refractive index change, having suitable features for large-scale integration, polarization independence, and wavelength insensitivity, is briefly summarized. Recent experimental results obtained by an optical switch module (OSM), comprising a packaged version of the 4 x 4 optical switch array with novel fiber arrays [APT (aligned by pyramidal throughholes) fiber arrays], are presented. Preliminary experimental results of module qualification and reliability obtained with the compact OSM are discussed. Finally, an optical asynchronous transfer mode (ATM) switching system architecture using the OSM as a key device is introduced, and high-speed pulse response characteristics of the OSM are examined for its application to the ATM switch system.

Electronic switching system software structure considering virtualizing technique and software components

AbstractThe stored‐program control system presently forms the main‐stream of the switching control system because of the flexibility in function modifications, compared with the wired‐logic hardware. One of the problems which has manifested recently is the large number of steps of the software modifications, which accompany with the modifications of the switching system architecture and the additions of functions. One of the major reasons for the large number of modification steps is the traditional modularisation, where the switching system architecture and the signaling systems are assumed to be retained. Because of this assumption, the modifications have to be made at various scattered points in the software systems, or have to be made at unexpected points, thereby increasing the number of steps in the modifications. This paper aims at improving the versatility of the software, and describes the modular breakdown, where the modification is localized by making the switching system architecture and the signaling system implicit and virtualized. By the same idea as in the hardware architecture, the software component technique is realized, where the program‐unit is subdivided into a set of units depending on the starting conditions of the programs and a set of units not depending on the starting conditions, and the module is composed by combining those two sets of units. By an example, it is shown that the proposed software architecture is useful.

Switching control multiprocessor system

AbstractA multiprocessor architecture for switching systems whose processing volumes increase with network function enhancement is discussed. This architecture allows individual processors to be added without endangering reliability by modifying the already installed multiprocessor system. Essential conditions for the architecture are: An example of switching control multiprocessor system based on this study result will be shown. (1) All network resources must be managed using common memory. (2) Switching control functions must be divided into signaling processing functions and call control processing functions to reduce the processing delay as much as possible. Call control processing functions must be equally shared by the call control processor. (3) Each signaling processor must be associated with a single signaling system.

A New Software Architecture for Switching Systems

Electronic switching systems were introduced in the mid1960's, and have since undergone constant modifications to provide new features, expand into new applications, and adapt to new hardware technologies. The increasing costs of software development have led to the need to reexamine the design concepts of present systems and define more cost-effective architectures. The specifications and derivation of a new modular switching system architecture which addresses the problems of constant change are discussed.

Microprocessor Application to Telephone Terminal Switching System Architecture

Microprocessor application to a switching system, especially to telephone terminals, is expected to change switching system architecture. From this viewpoint, Basic Experimental Switching System (BESS) is designed as a functionally distributed control switching system accommodating intelligent terminals. This paper describes BESS hardware and software structures. BESS has the following characteristics. 1) Microprocessor controlled terminals can store and forward dialed digits, and can exchange data between them. Almost all services can be realized merely by a program stored in each terminal itself. 2) Functionally distributed controller of only three untailored microprocessors can treat 100 basic calls. 3) Program flexibility is especially realized by distinct exchange program separation into algorithm, data management and network control parts.