Architecture For Real-time Processing Research Articles

A Novel Real-Time Echo Separation Processing Architecture for Space–Time Waveform-Encoding SAR Based on Elevation Digital Beamforming

Space–time waveform-encoding (STWE) SAR can receive echoes from multiple sub-swaths simultaneously with a single receive window. The echoes overlap each other in the time domain. To separate the echoes from different directions, traditional schemes adapt single-null steering techniques for digital receive beam patterns. However, the problems of spaceborne DBF-SAR, in practice, such as null extension loss, terrain undulation, elevation angle of arrival extension, and spaceborne antenna beam control, make the conventional scheme unable to effectively separate the echoes from different sub-swaths, which overlap each other in the time domain.A novel multi-null constrained echo separation scheme is proposed to overcome the shortcomings of the conventional scheme. The proposed algorithm can flexibly adjust the width of the notch to track the time-varying pulse extension angle with less resource consumption. Moreover, the hardware implementation details of the corresponding real-time processing architecture are discussed. The two-dimensional simulation results indicate that the proposed scheme can effectively improve the performance of echo separation. The effectiveness of the proposed method is verified by raw data processing instance of an X-band 16-channel DBF-SAR airborne system.

Demonstration of Intermediate Frequency Digital Beamforming With X-Band and C-Band DBF-SARs

High-resolution wide swath (HRWS) imaging has become a research hotspot in the field of synthetic aperture radars (SARs) in recent years. Digital beamforming (DBF) denotes a powerful technique for obtaining the HRWS images. The DBF can be implemented in a spaceborne SAR in real time but at the cost of massive digital resources. To solve this problem, an intermediate frequency (IF) DBF real-time processing architecture has been proposed, but it has never been validated in practice. In this letter, the X-band 16-channel DBF-SAR and the C-band four-channel DBF-SAR are used to demonstrate the effectiveness of the IFDBF scheme in practice for the first time. The performance of the IFDBF scheme is verified by the detailed analysis of the signal-to-noise ratio (SNR) improvement and system complexity. The result shows that the IFDBF scheme can achieve the same SNR improvement as the DBF scheme. Moreover, by applying the IFDBF scheme, a spaceborne SAR can save more digital resources in real-time processing.

A Novel Weight Generator in Real-Time Processing Architecture of DBF-SAR

Digital beamforming (DBF) with scan-on-receive (SCORE) technique in elevation is a powerful technique that enables a spaceborne synthetic aperture radar (SAR) to achieve high-resolution wide swath (HRWS) imaging. In the spaceborne DBF-SAR system, sampling signals from each channel are weighted by weights generated by a digital signal processing system in real-time. However, the contradiction between the shortage of spaceborne hardware resources and resource demand of the multichannel real-time signal processing increases the difficulty of system design. In order to solve this problem, a novel weight generator and an improved intermediate frequency (IF) DBF real-time processing architecture are proposed in this article. By taking advantage of the special properties of the SCORE algorithm, the proposed weight generator calculates weights using a linear polynomial algorithm. The simulation result shows that a low-order approximation can achieve high performance. The proposed generator can correct multichannel amplitude and phase error at a low cost on hardware resources. The effectiveness of the proposed method is verified by experiments with a raw data processing instance of an X-band 16 channels DBF-SAR.

A Cloud-Based Platform for Big Data-Driven CPS Modeling of Robots

This paper proposes an improved cyber-physical systems (CPS) architecture for a smart robotic factory based on an industrial cloud platform driven by big data based on the traditional CPS architecture. This paper uses the architecture analysis and design language to model and design a total of three scales for the underlying cell-level robot, the system-level robot shop, and the overall robotic smart factory CPS, respectively, to complete the conceptual scheme for building a robotic smart factory from a local to an overall CPS system. Using the advantages of cloud computing and combining robotic CPS with cloud computing, an architecture for an industrial management system for CPS cloud computing is proposed. Base based distributed storage architecture with Storm based distributed real-time processing architecture. In terms of modeling, the advantages and disadvantages of using AADL, structural analysis, and design language, and modelers, a physical device modeling language, are combined to analyze the advantages and disadvantages of architecture analysis & design language (AADL) for modeling CPS and propose a CPS analysis and design based on AADL and applicable to it. The paper also investigates the use of LeNet models for state identification in the HSV color space. The algorithm was verified on a self-built power equipment indicator dataset with a 100% detection rate and 99.8% state recognition accuracy after four consecutive frames of fusion detection. Simulink simulation of the trolley was carried out in terms of a cell-level robotic trolley CPS system to demonstrate the effectiveness of the design of a robotic CPS system driven by soaring data based on the industrial cloud platform proposed in this paper.

A Real-Time Entity Monitoring based on States and Scenarios

Scenario: The current markets require online processing and analysis of data as soon as they arrive to make decisions or implement actions as soon as possible. PAbMM is a real-time processing architecture specialized in measurement projects, where the processing is guided by measurement metadata derived from a measurement framework through the project definition. Objective: To extend the measurement framework incorporating scenarios and entity states as a way to online interpret the indicator’s decision criteria according to scenarios and entity states, approaching their conditional likelihoods. Methodology: An extension based on entity and context states is proposed to implement scenarios and entity states. A memory structure based on the occurrence matrix is defined to approach the associated conditional likelihoods while the data are processed. A new hierarchical complimentary schema is introduced to foster the project definition interoperability considering the new concepts. An extension of the cincamipd library was carried forward to support the complementary schema. An application case is shown as a proof-of-concept. Results: A discrete simulation is introduced for describing the times and sizes associated with the new schema when the volume of the projects to update grow-up. The results of the discrete simulation are very promising, only 0.308 seconds were necessary for updating 1000 active projects. Conclusions: The simulation provides an applicability reference to analyse its convenience according to the project requirements. This allows implementing scenarios and entity states to increase the suitability between indicators and decision criteria according to the current scenario and entity state under analysis.

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery.

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited.

Real-Time Processing System for the JET Hard X-Ray and Gamma-Ray Profile Monitor Enhancement

The Joint European Torus (JET) is currently undertaking an enhancement program, in which one of the objectives is to test relevant diagnostics for the International Thermonuclear Experimental Reactor (ITER), the reference for the next generation of fusion experiments. One of the challenges in ITER is the provision of real-time data analysis and compression capabilities, to sustain the expected long duration discharges and the high acquisition rates achieved by recent data acquisition systems. Foreseeing this real-time requirement, a new system was developed and installed at JET for the gamma-ray and hard X-ray profile monitor diagnostic. The new system, which is connected to 19 CsI(Tl) photodiodes in order to obtain the line-integrated profiles of the gamma-ray and hard X-ray emissions, was designed to overcome the data acquisition limitations of the present fast electron Bremsstrahlung diagnostic (FEB), while exploiting the required real-time features. This paper presents the real-time processing architecture for the JET gamma-ray and hard X-ray profile monitor. The system hardware, based on the Advanced Telecommunication Computer Architecture (ATCA) standard, includes reconfigurable digitizer modules with embedded Field Programmable Gate Array (FPGA) devices capable of acquiring and simultaneously processing data in real-time from the 19 detectors. A suitable algorithm was developed and implemented in the FPGAs, which are able to deliver the corresponding energy of the acquired pulses, and its associated occurrence time. The real-time processed data is sent periodically, during the discharge, through the JET real-time Asynchronous Transfer Mode (ATM) network, and stored in the JET scientific databases at the end of the pulse. Publishing the processed data in the ATM network enables it to be used for machine control purposes (e.g. the information about the line-integrated emissions of the hard X-rays in real time can be used to determine the lower hybrid current drive deposition before the main heating phase). Additionally, the real-time processed data is used for local calibration, using embedded radioactive sources to build in real-time the 19 channels spectra. The acquired raw data is also stored in the digitizer modules' local memory and retrieved after the pulse to the JET database, where it can be post-processed offline to validate the real-time algorithms. The interface between the ATCA digitizers, the JET Control and Data Acquisition System (CODAS) and the JET real-time network is provided by the Multithreaded Application Real-Time executor (MARTe). From the experimental results it was concluded that it is possible to measure in real-time the line-integrals of both hard X-ray and gamma-ray emissions, covering energy range from ∼200 keV to 8 MeV. This allows us to meet two of the major milestones: the ability to process and supply high volume data rates in real-time over a wide spectrum energy range.

Data Fusion Framework: concurrent architecture for real-time processing

In the last few decades, a new way of interpreting multi-sensor array processing techniques and artificial intelligence systems has been introduced. This theory focuses on interactions and fusion between heterogeneous/homogeneous information at different layers in order to guarantee data completeness and robust resolution of hard-to-solve problems. Our research investigates this theory, well known as Data Fusion (DF). In this paper, we present an operating framework that permits DF during the elaboration flow at different levels of computation. We focused our attention on several key aspects of real-time implementation.

A High Speed VLSI Architecture for Handwriting Recognition

This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC. HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).

Design and demonstration of a real time processor for one-bit coded SAR signals

Real-time on-board SAR processing represents a useful tool for airborne and spaceborne microwave remote sensing. The authors present the design together with a prototype realisation of a real-time processing architecture for one-bit coded SAR signals, with reference to the German airborne experimental-SAR (E-SAR) system. Since the input data of this implementation are binary sequences, it is more convenient to operate in the time domain using very simple and low cost devices, integrable on motherboards of small dimensions, requiring small DRAM memory buffers, and absorbing very low power. The prototype has been realised in field programmable gate array (FPGA) integrated logic. Experimental results have shown its capability of producing one-look images in real time on board the aircraft.

Zero waiting-cycle hierarchical block matching algorithm and its array architectures

A new hierarchical block matching algorithm with a novel arrangement of data flow is proposed. Its speed can be as fast as that of the conventional hierarchical block matching algorithms and its prediction quality is very close to the full search algorithm. In order to implement this algorithm, a multiprocessor array architecture for real-time processing is proposed. Due to the novel arrangement of data flow, the limitations of conventional ones will no longer exist. Moreover, the hardware complexity, size of local memory, input bandwidth, and speed performance of the proposed architecture are also analyzed. Finally, the simulation results are given to demonstrate the effectiveness of this new algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Highly Available Multimicroprocessor System for Real-Time Applications

This paper describes the implementation of a highly available multimicroprocessor system based on the M.A.R.A. (Modular Architecture for Real Time Processing) multimicroprocessor architecture developed by Selenia. The proposed solution is based on the full duplication of a M.A.R.A. node. Fault detection is independently performed on the two nodes. At every time, only one of the two nodes (Master Node) controls the application, while the other node (Slave Node) is always ready to substitute the Master node. In case of a detected fault, the Master node communicates its unavailability to the Slave Node, and disconnects itself from the application. The Slave Node resumes the control of the application starting from the most recent consistent system state. To avoid any loss of application, the Slave Node during normal operation continuously maintains and updates a copy of the system state on the basis of informations provided to it by the Master Node. The application software is structured in atomic transactions. An atomic transaction is intended as a set of actions which updates the system state so that either all the actions have been executed (transaction commit), or none will have been (transaction abort). Therefore in case of a fault in the Master Node, the consistent system state is resumed by the Slave Node by aborting the not yet committed transactions and restoring them; it also completes the commit phases of the transactions which were committing in the Master Node when the fault has happened. The application software is supported by a run-time environment which makes transparent the duplicated configuration of the system.