Architecture For Real-time Image Processing Research Articles

Special issue on reconfigurable architecture for real-time image processing

The performance requirements of image processing applications have led to increase in the computing power of implementation platforms, in particular when real-time constraints are to be met. Image processing applications may consist of different standards, or different algorithms used at different stages of the processing chain. The computing paradigm of reconfigurable architectures promises a trade-off between flexibility and performance. Reconfigurable architectures can exploit fine-grain (more suitable for low-level and medium-level operations in the image processing chain) and coarse-grain parallelism (more suitable for high-level operations in the image processing chain). Many reconfigurable architectures have been constructed specifically for image processing using different processors and dedicated circuits such as ASICs and FPGAs. This special issue on Reconfigurable Architecture for Real-Time Image Processing presents articles addressing reconfigurable computing for real-time image processing, programming frameworks with FPGA-style mapping as well as real-time and embedded image processing applications and implementations. This special issue includes nine papers that are briefly outlined below: The first paper, by Denoulet and Merigot, presents a massively parallel SIMD architecture based on reconfigurability and asynchronism called Associative Mesh. The introduced virtualized associative mesh achieves real-time execution for split and merge segmentation, watershed segmentation and motion detection. The second paper, by Kessal, Karabernou and Demigny, focuses on the Ardoise project. The goal of this project is to realize a dynamically reconfigurable platform. This paper proposes a methodology that can be easily adapted to common SoC architecture. The third paper, by Sen, Hemaraj, Plishker, Shekhar and Bhattacharya, presents a novel architecture that enables dynamically-reconfigurable image registration. It also addresses some data-flow-motivated parallel architectures for image registration. The fourth paper, by Meng, Freeman, Pears and Bailey, details the implementation of a human action recognition system on a reconfigurable, FPGA based video processing architecture. The fifth paper, by Jiang, Crookes and Bouridane, describes a parallel-matching processor architecture to perform high-speed biometric fingerprint database retrieval. The processor was implemented on Xilinx Virtex-E and runs up to 65 MHz. The sixth paper, by Chandrasekaran, Amira, Minghua and Bermak, covers the presentation of an architecture for the Finite Ridgelet Transform. It presents a parallel architecture as well as FPGA and ASIC implementations. The seventh paper, by Srinam and Eng, presents various implementations of the Kolmogorov phase screen generator. The FPGA hardware implementation provides a speedup of more than 60 times of the original algorithm. The eight paper, by Saponara, Casula and Fanucci proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. The ninth paper, by Seetharaman, Venkataramani and Lakshminarayanan, describes how to get the benefits of M. Akil (&) Department of Computer Science, Institut Gaspar-Monge, Unite mixte de recherche CNRS-UMLVPE-ESIEE (UMR 8049), ESIEE, Cite Descartes, BP 99, 93162 Noisy-le-Grand Cedex, France e-mail: akilm@esiee.fr

New multi-DSP parallel computing architecture for real-time image processing

The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.

Linear array processors with multiple access modes memory for real-time image processing

This paper presents the linear array processors with multiple access modes memory system (LAPMAMM), an efficient mono-dimensional parallel architecture for real-time image processing. This architecture is composed of n processors and n 2 memory modules. These memory modules have multiple access modes: RAM, FIFO, normal CAM and interactive CAM modes. They are associated to a linear array of VLIW processors which are interconnected using a simple tree network that ensures an O(log( n)) data propagation time. The practical working of the architecture is explained using the example of a labeling algorithm developed for LAPMAMM. A hardware simulation of a LAPMAMM prototype has been carried out to test its performance in low and intermediate level image processing. The simulation results of the VHDL model are presented.

A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant

In this paper, we present a VLSI architecture for real-time image processing in quality control industrial applications: automation of the visual inspection phase of mechanical parts treated by the Fluorescent Magnetic Particle Inspection method for structural-defect detection. The VLSI architecture implements a highly constrained neural network tailored for this specific application: the multi-layer perceptron with strictly local connections. The learning of the weights is performed off line by using the adaptive simulated-annealing algorithm. The neural network has been trained on real plant data: recognition results of the training and classification tasks compare favorably with those obtained by expert human operators.The VLSI architecture receives as input the image (taken on-line on the plant) of a mechanical part and it will find out if at least one structural surface defect is present. The VLSI architecture was optimized, through a set of transformations on the high-level VHDL specifications of the neural network algorithm, to reach real-time operating conditions. Following the proposed approach and the designed architecture, we designed and successfully tested a custom VLSI chip for the real-time implementation of the recognition task.