Timing Constraints Of Applications Research Articles

PC7. Competency-based, Time-variable Resident Education: A Programmatic Update

PURPOSE: In 2018, the University of Pittsburgh Medical Center (UPMC) adopted a Competency-Based, Time-Variable (CBTV) model for plastic surgery training, the first of its kind in the United States. This educational model emphasizes performance and skill mastery, rather than time-based benchmarks, as the measure by which residents are deemed fit for graduation. METHODS: Starting in the PGY1 year, each resident is evaluated regularly via oral exam to assess knowledge of plastic surgery principles. Resident self-assessment of technical competency is directly compared to faculty assessment utilizing the Zwisch Rating Scale, a validated scoring system in rating resident autonomy. Our department has reorganized its rotation schedule to shift Chief-level rotations from the PGY6 year to the PGY5 year. RESULTS: UPMC matched its first CBTV resident class in 2018. Of this three-resident cohort, two residents (66%) were deemed competent for graduation after five clinical years of training. One resident elected to defer graduation until after six years of training due to fellowship application timing constraints. The other resident elected to pursue a year of research and subsequently graduate after five clinical years of training. Thus, all three residents will graduate after six years at UPMC, but with customized experiences based on their specific interests and educational needs. CONCLUSION: The CBTV model has increased the flexibility of our training program to accommodate individualized educational needs of each resident, allowing them variable rotation schedules to address surgical deficiencies as well as to further develop their clinical interests. This is a paradigm shift in surgical education.

ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems

Reinforcement learning (RL), specifically Q-learning, with human-like learning abilities to learn from experience without any a priori data, is being increasingly used in embedded systems in the field of control and navigation. However, finding the optimal policy in this approach can be highly compute-intensive, and a software-only implementation may not satisfy the application's timing constraints. To this end, we propose optimization methods at multiple levels of accelerator design for RL. Specifically, at the architecture-level, we exploit the instruction-level parallelism and the spatial parallelism in FPGAs to improve the throughput over state-of-the-art designs by up to 34%. Further, we propose lookup table-level optimizations to reduce the resource utilization and power dissipation of the accelerator. Finally, we propose algorithm-level approximation that can be used for acceleration of Q-learning problems with more states and for reducing the peak power dissipation. We report up to 10× reduction in power dissipation with marginal degradation in quality of results.

Dependency-Aware Task Scheduling in Vehicular Edge Computing

Vehicular edge computing (VEC) offers a new paradigm to improve vehicular services and augment the capabilities of vehicles. In this article, we study the problem of task scheduling in VEC, where multiple computation-intensive vehicular applications can be offloaded to roadside units (RSUs) and each application can be further divided into multiple tasks with task dependency. The tasks can be scheduled to different mobile-edge computing servers on RSUs for execution to minimize the average completion time of multiple applications. Considering the completion time constraint of each application and the processing dependency of multiple tasks belonging to the same application, we formulate the multiple tasks scheduling problem as an optimization problem that is NP-hard. To solve the optimization problem, we develop an efficient task scheduling algorithm. The basic idea is to prioritize multiple applications and prioritize multiple tasks so as to guarantee the completion time constraints of applications and the processing dependency requirements of tasks. The numerical results demonstrate that our proposed algorithm can significantly reduce the average completion time of multiple applications compared with benchmark algorithms.

A Fault-Tolerant Scheduling Algorithm Based on Checkpointing and Redundancy for Distributed Real-Time Systems

Real-time systems are becoming ever more widely used in life-critical applications, and the need for fault-tolerant scheduling can only grow in the years ahead. This article presents a novel fault tolerance approach for tolerating transient faults in hard real-time systems. The proposed approach combines both checkpointing with rollback and active replication to tolerate several transient faults. Based on this approach, a new static fault-tolerant scheduling algorithm SFTS is presented. It is based on a list of scheduling heuristics which satisfy the application time constraints even in the presence of faults by exploring the spare capacity of available processors in the architecture. Simulation results show the performance and effectiveness of the proposed approach compared to other fault-tolerant approaches. The results reveal that in the presence of multiple transient faults, the average timing overhead of this approach is lower than checkpointing technique. Moreover, the proposed algorithm SFTS achieves better feasibility rate in the presence of multiple transient faults.

Efficient and scalable execution of smart city parallel applications

SummaryRecent research efforts in the field of urban computing aim to develop innovative services for citizens through the application of ubiquitous and pervasive computing paradigms in urban spaces. Smart city applications need to cope with a large number of involved users and devices. Since data and objects are strictly related to the territory on which they are defined and used, it is preferable, when possible, to perform computation locally through the adoption of dispersed computing nodes such as CPU‐equipped sensors. In this context, the computation related to smart city applications can be profitably and efficiently parallelized by partitioning the territory into regions and assigning the computation related to each single region to a local node. Nevertheless, the adoption of parallel computing models poses several communication and synchronization issues, especially when the number of nodes is large and the time constraints of applications are compelling. This paper presents and analyzes a parallel computing model for smart city applications in which each node needs to exchange information only with a subset of neighbor nodes, allowing the synchronization overhead to be significantly reduced. As sample application, we consider the analysis and prediction of internet traffic generated by vehicle and pedestrian devices moving on a smart avenue equipped with distributed computing nodes. This work offers a detailed performance evaluation in a number of scenarios, including uniform and nonuniform user distribution and different types of user mobility behavior. The results show that the presented computation model offers notable advantages in terms of computation efficiency and speedup, with respect to a classical all–to‐all synchronization paradigm, in which the nodes need to coordinate with a central entity.

Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane

Transient errors are a major concern for the correct operation of low-level cache memories. Aggressive integration requires effective mitigation of such errors, without extreme overheads in power, timing, or silicon area. We demonstrate a hybrid (hardware-software) scheme that mitigates bit flips in data that reside in low-level caches. The methodology is shown to be applicable in streaming applications and we illustrate that with a video decoding case study on a state-of-the-art many-core chip. The single-chip cloud computer is an experimental processor created by Intel Labs. Dedicated on-chip memories are utilized to keep safe copies for key application data, thus allowing rollbacks upon error detection. The experimental results illustrate the tradeoff between application delay, consumed energy, and output fidelity as the injected errors are corrected. When output fidelity is considered as a hard constraint, application slack used for mitigation can be reclaimed with dynamic frequency scaling. Output fidelity is guaranteed regardless of the error injection intensity and the application's timing constraints are respected up to a certain upper bound of error injection.

Design space exploration for partially reconfigurable architectures in real-time systems

In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area improvement up to 38% on some resources without compromising application performance, in a very small amount of time: less than 30s.

A Proficient Thermal Based Prediction Unit in Multi Core System

Multi core system has become a popular Execution platform for many Real time systems. The system is continue to shrink down due to thermal hotspots and temperature gradients, which Are significantly impact system parameters like Reliability, performance, cost and leakage power To improve these parameters in Real time systems/ multi core system a Temperature prediction management (TPM) technique is required for mission/safety critical application running on a multi core chip to avoid possible thermal hazards while meeting the application timing constraints. In this paper, we propose an efficient framework for Temperature prediction management (TPM) with time constraint model (Tracker & WDT) in many core systems where the balanced thermal profile can be achieved by proactive task migration among neighboring cores. And based on temperature prediction unit task migration will be performed among neighboring processing elements. Compared with existing proactive task migration technique ,our approach effectively minimize the thermal hotspots, less migration overhead with negligible performance overhead and it increase the processing speed of multi core systems.

Modular software architecture for flexible reservation mechanisms on heterogeneous resources

Management, allocation and scheduling of heterogeneous resources for complex distributed real-time applications is a challenging problem. Timing constraints of applications may be fulfilled by the proper use of real-time scheduling policies, admission control and enforcement of timing constraints. However, it is not easy to design basic infrastructure services that allow for easy access to the allocation of multiple heterogeneous resources in a distributed environment. In this paper, we present a middleware for providing distributed soft real-time applications with a uniform API for reserving heterogeneous resources with real-time scheduling capabilities in a distributed environment. The architecture relies on standard POSIX OS facilities, such as time management and standard TCP/IP networking services, and it is designed around CORBA, in order to facilitate modularity, flexibility and portability of the applications using it. However, real-time scheduling is supported by proper extensions at the kernel-level, plugged within the framework by means of dedicated resource managers. Our current implementation on Linux supports the reservation of the CPU, disk and network bandwidth. However, additional resource managers supporting alternative real-time schedulers for these resources, as well as additional types of resources, may be easily added. We present experimental results gathered on both synthetic applications and a real multimedia video streaming case study, showing the advantages deriving from the use of the proposed middleware. Finally, overhead figures are reported, showing the sustainability of the approach for a wide class of complex, distributed, soft real-time applications.

Parallelisation of the particle filtering technique and application to Doppler-bearing tracking of maneuvering sources

Particle filtering may cope with non-linear and/or non-Gaussian models. As a counterpart, this technique suffers from an heavy computation cost and cannot always satisfy the real time constraints of applications. A data parallel algorithm is proposed to achieve real-time particle filtering. Extensive results are presented in the passive SONAR tracking context for maneuvering targets.

A Haptic Assembly and Disassembly Simulation Environment and Associated Computational Load Optimization Techniques

There exist a large body of work in the field of assembly, sometimes involving the use of a virtual environment to assist the user in assembly analysis. Typically, these environments limit the user’s interaction with the environment to one sense, sight, and two dimensions, the table upon which the mouse rests. The introduction of a haptic interface into the computer-aided design environment allows users to incorporate both a third dimension and a second sense, that of touch, into their work. In this paper, the development of an application called HIDRA (Haptic Integrated Dis/Re-assembly Analysis) is discussed, which integrates haptic feedback into an assembly/disassembly simulation environment. In particular, the focus is on the computer architecture developed to support such haptic simulations and the methods that have been created to meet some of the application time constraints unique to haptic simulation. Although focused on assembly and disassembly simulations, these issues and developments are relevant for the broader development of haptically enabled simulations in general.

Towards Task Dynamic Reconfiguration over Asymmetric Computing Platforms for UAVs Surveillance Systems

High-performance platforms are required by modern applications that make use of massive calculations. Actually, low-cost and high-performance specific hardware (e.g. GPU) can be a good alternative along with CPUs, which turned to multiple cores, forming powerful heterogeneous desktop execution platforms. Therefore, self-adaptive computing is a promising paradigm as it can provide flexibility to explore different computing resources, on which heterogeneous cluster can be created to improve performance on different execution scenarios. One approach is to explore run-time tasks migration among node's hardware towards an optimal system load-balancing aiming at performance gains. This way, time requirements and its crosscutting behavior play an important role for task (re)allocation decisions. This paper presents a self-rescheduling task strategy that makes use of aspect-oriented paradigms to address non-functional application timing constraints from earlier design phases. A case study exploring Radar Image Processing tasks is presented to demonstrate the proposed approach. Simulations results for this case study are provided in the context of a surveillance system based on Unmanned Aerial Vehicles (UAVs).