VLSI Circuit Applications Research Articles

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Deep Neural Learning based Deming Regression Adder Enhancement on Digital Multiplier for 3D Graphical Applications in VLSI Circuits

This work aims to investigate 3D Technology to provide better performance enhancement for several generations. The three-dimensional integrated circuit allows better integration density, faster on-chip communications, and heterogeneous integration. The goal of this research is to reduce time consumption and power consumption by introducing the Deep Neural Learnt Deming Regression Based Ladner-Fisher Adder Enhancement (DNLDR-LFAE) Technique in VLSI circuits. Input information (carry inputs) is taken for input layer and transmits to hidden layer 1. Deeming regression analysis has performed at hidden layer 1 to pre-process input data and it is send to hidden layer 2. In that layer, performs carry generation as well as post-processing as well as output outcomes have enclosed with convolution. Finally, at output layer, outcomes were attained to execute well-organized adder improvement of digital multiplier by lesser power as well as time consumption. DNLDR-LFAE Technique measured in terms of power, location and time consumption. An outcome of DNLDR-LFAE Technique decreases time and power consumption of adder enhancement than other methods. The hardware complexity of proposed technique obtains minimized by upto 52% to 63% when designed by Ladner-Fisher Adder.

A transformation algorithm to construct a rectangular floorplan

A rectangular floorplan (RFP) is a partition of a rectangle R into rectangles R1,R2,…,Rn such that no four of them meet at a point. Rectangular floorplans find their applications in VLSI circuits floorplanning and architectural floorplanning. Let G represent the graph of a rectangular floorplan RFP1(n) and H be a subgraph of G, where n denotes the number of rectangles in RFP1(n). It is well known that every subgraph of G may not admit an RFP, i.e., G does not have a hereditary property. Hence, in this paper, we first derive a necessary and sufficient condition for H to admit a rectangular floorplan RFP2(n). Further, if H admits an RFP, we present a linear time transformation algorithm for deriving RFP2(n) from RFP1(n).

Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.

Design of High Speed and Low-Power NOR Based Dynamic CMOS PLA for Logic Function Realization

This paper presents the design of dynamic CMOS PLA for high speed and low power VLSI circuit applications. The design has been carried out based on NOR function. The PLA has been implemented to realize 3 input logic functions using MOS transistor having channel length of 150nm . The circuit is simulated with the help of T-SPICE tools. According to ITRS currently VLSI circuits are designed at power supply voltage (VDD) of ≤ 1 V. In this paper the PLA has been simulated at VDD of 1 V. However the overall power consumption and gate delay of the circuit has been reported for the VDD from 0.5-1.2 V. The power consumption and gate delay of the order of nW and PS respectively. Compared to recent literature in the relevant area our work presented in this paper is also meet the high speed and low power VLSI circuit applications.

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substrates for future high power RF applications

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance of 1050 mS/mm, current gain cut-off frequency of 350 GHz and power gain cut-off frequency of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density and breakdown voltage are 1580 cm2/(V s), , and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.

DC and microwave characteristics of 20 nm T-gate InAlN/GaN high electron mobility transistor for high power RF applications

The DC and microwave characteristics of 20 nm gate length (Lg) InAlN/GaN High electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have investigated for both depletion mode (D-mode) and Enhancement mode (E-mode) operation using Synopsys TCAD tool. The simulation is performed at room temperature by using drift-diffusion model. The device having the features of recessed T - gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed novel Lg = 20 nm, W = 2 × 40 μm D-mode (E-mode) HEMT exhibited a peak drain current density (Idmax) of 2.7 (2.6) A/mm, transconductance (gm) of 1.04 (1.63) S/mm, current gain cut-off frequency (ft) of 310 (343) GHz and power gain cut-off frequency (fmax) of 364 (236) GHz. The measured carrier mobility (μ), sheet charge carrier density (ns) and breakdown voltage are 1580 (1615) cm2/V−s, 1.9 × 1013 (1.93) Cm−2 and 10.7 (12.8) V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future sub-millimetre wave high power RF VLSI circuit applications.

Performance modeling and analysis of carbon nanotube bundles for future VLSI circuit applications

In this work, we have presented a comprehensive analysis of the performance of copper (Cu) and existing carbon nano tube (CNT) bundle structures (i.e. SWCNT, DWCNT and MWCNT) across nanometer technology nodes like 45, 32, 22 and 16 nm at local, intermediate and global level interconnects. Double walled carbon nano tubes (DWCNTs) and multi walled carbon nano tubes (MWCNTs) are modeled like simple single walled carbon nano tube (SWCNT) equivalent model with high accuracy. The analytical closed form delay expressions for SWCNT, DWCNT and MWCNT bundles have been found out. It has been observed that sparse SWCNT bundle interconnects show about 50 % performance improvement for 20 $$\upmu $$ μ m long local level interconnects over Cu in 16 nm technology node, whereas the performance advantage numbers for MWCNT and sparse DWCNT bundles are 50 and 35 % respectively. For 200 $$\upmu $$ μ m long intermediate level interconnects, the performance advantage numbers are 85, 80 and 75 % for dense SWCNT, MWCNT and dense DWCNT bundles respectively in 16 nm node. For 10 mm long global level interconnects, the performance advantage numbers are 85, 85 and 75 % for dense SWCNT, MWCNT and dense DWCNT bundles respectively in 16 nm node. It is also observed that the performance numbers improve with scaling for all levels of interconnects. It is also shown that the ratio of delay of CNT bundles and Cu for various levels of interconnects agree well with the existing work.

Inclusion-exclusion principle in the design of a BIST unit for LSI and VLSI circuits

The basic inclusion-exclusion algorithm is considered in the context of binary vectors. A connection is revealed between the algorithm and the generation of convolution codes for BIST applications in LSI and VLSI circuits. A strategy for changing from combinatorial identities to theoretical probabilities (with infinitely many vectors) is used to extend some classical relations of discrete mathematics and to investigate the results from the viewpoint of signature synthesis. It is shown that the inclusion-exclusion approach is not an identification algorithm in its own right, as it essentially gives the sum of i empirical probabilities.

Low-power design techniques for scaled technologies

Scaling of transistor feature sizes has provided a remarkable advancement in silicon industry for last three decades. However, while the performance increases due to scaling, the power density increases substantially every generation due to higher integration density. Furthermore, the demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power-efficient design techniques has grown considerably. Several efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI circuit applications. In this paper, we discuss different circuit techniques that are used to maintain the power consumption (both static and dynamic) within a limit while achieving the highest possible performance.

Overview of complementary GaAs technology for high-speed VLSI circuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 /spl mu/W/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor.

Differential BiCMOS logic circuits: fault characterization and design-for-testability

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated. >

Silicides and local interconnections for high-performance VLSI applications

As the minimum VLSI feature size continues to scale down to the 0.1–0.2-µm regime, the need for low-resistance local interconnections will become increasingly critical. Although reduction in the MOSFET channel length will remain the dominant factor in achieving higher circuit performance, existing local interconnection materials will impose greater than acceptable performance limitations. We review the state-of-the-art salicide and polycide processes, with emphasis on work at IBM, and discuss the limitations that pertain to future implementations in high-performance VLSI circuit applications. A brief review of various silicide-based and tungsten-based approaches for forming local interconnections is presented, along with a more detailed description of a tungsten-based “damascene” local interconnection approach.

Characterisation of furnace-annealed TiSi2 for VLSI circuit applications

Abstract The incorporation of a furnace-annealed titanium silicide into a CMOS process is discussed. The titanium silicide is self-aligned to the gate and source/drain areas and the process modules required for this method are shown. This process was used to fabricate CMOS devices and the test results presented show electrical characteristics comparable with those obtained from non-silicided devices. The use of ion beam mixing to improve silicide formation is examined and the resulting device characteristics are presented.

Evaluation of the Selective Tungsten Deposition Process for VLSI Circuit Applications

Tungsten films have been selectively deposited on oxide‐patterned silicon wafers using two successive deposition steps, i.e., the Si reduction of followed by the reduction of . The deposition process was performed in a horizontal hot wall LPCVD reactor. In this reactor, the surface of vertical wafers was parallel to the axis of the quartz tube. The thickness of W films obtained for a given deposition time was found to be dependent on the “history” (or the cleanliness) of the CVD reactor. The thickness uniformity across a wafer and from wafer to wafer was determined as a function of the wafer position in the CVD reactor. The selectivity of the process was evaluated by measuring the W nuclei density on the oxide (PSG) mask as a function of the thickness of W films. During the validity period of the CVD reactor, tungsten films of 220 nm in thickness were produced on 12 wafers per run with undetectable W nuclei on the mask (perfect selectivity). The CVD reactor appears to be suitable for selective deposition of W films used as diffusion barriers in Al/W/Si contact structures.

Mo/TiW contact for VLSI applications

A molybdenum and titanium-tungsten double-layer contact metallization was developed for VLSI circuit applications. A thin TiW contact layer produced good ohmic contact and thermal stability With n+silicon and p+silicon up to 650°C without spiking. Thick Mo over the TiW layer has high conductivity, good step coverage, low electromigration, and smooth surface morphology. Both metal layers are sequentially sputtered in one pumpdown. The pattern formation process, including the etching Of approximately 1-µm-size contacts and tightly pitched 1.5-µm-wide metal lines is described. The contact resistance was evaluated as a function of processing conditions and high-temperature annealing. The contact resistance values for n+silicon contacts were always less then 35 Ω . µm2and that for the p+silicon contact resistance was within a range of 35 to 85 Ω . µm2after annealing at 400°C. Annealing experiments showed that occasional larger values of p+contact rsistance could be reduced by annealing at 625°C. There was no junction leakage degradation for annealing temperatures below 600°C. The mechanism, and cause, of the contact resistance and leakage current change with sintering temperature was studied by means of X-ray, SIMS, TEM, and SEM.