Design Automation Applications Research Articles

Implementation of Text to Image using Diffusion Model

Text-to-image generation is a transformative field in artificial intelligence, aiming to bridge the semantic gap between textual descriptions and visual representations. This presents a comprehensive approach to tackle this challenging task. Leveraging the advancements in deep learning, natural language processing (NLP), and computer vision, this proposes a cutting-edge model for generating high-fidelity images from textual prompts. Trained on a vast and varied dataset of written descriptions and related images, this model combines an image decoder and a text encoder within a hierarchical framework. To enhance realism, this incorporates attention mechanisms and fine-grained semantic parsing. The model's performance is rigorously evaluated through both quantitative metrics and qualitative human assessments. Results demonstrate its ability to produce visually compelling and contextually accurate images across various domains, from natural scenes to specific object synthesis. This further explores applications in creative content generation, design automation, and virtual environments, showcasing the potential impact of our approach. Additionally, this releases a user-friendly API, empowering developers and designers to integrate our model into their projects, and fostering innovation and creativity. Key Words: image generation model, Deep learning, Natural language processing.

MeshPointNet: 3D Surface Classification Using Graph Neural Networks and Conformal Predictions on Mesh-Based Representations

Abstract In many design automation applications, accurate segmentation and classification of 3D surfaces and extraction of geometric insight from 3D models can be pivotal. This paper primarily introduces a machine learning-based scheme that leverages graph neural networks for handling 3D geometries, specifically for surface classification. Our model demonstrates superior performance against two state-of-the-art models, PointNet + + and PointMLP, in terms of surface classification accuracy, beating both models. Central to our contribution is the novel incorporation of conformal predictions, a method that offers robust uncertainty quantification and handling with marginal statistical guarantees. Unlike traditional approaches, conformal predictions enable our model to ensure precision, especially in challenging scenarios where mistakes can be highly costly. This robustness proves invaluable in design applications, and as a case in point, we showcase its utility in automating the computational fluid dynamics meshing process for aircraft models based on expert guidance. Our results reveal that our automatically generated mesh, guided by the proposed rules by experts enabled through the segmentation model, is not only efficient but matches the quality of expert-generated meshes, leading to accurate simulations.

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA)

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA)

DeepPlacer: A custom integrated OpAmp placement tool using deep models

Mechanisms towards the automatic analog integrated circuit layout design have been an intensive research topic in the past few decades. Still, the industrial environment has no automatic approach established. The advances of machine learning applications in electronic design automation come with the promise to change this reality. This paper proposes a deep learning generative model for the placement “optimization” of analog integrated circuit basic blocks. The model behaves as an argmin operator for the placement cost function and can provide placement solutions instantly. Moreover, the model can be fed with unlabeled data, greatly facilitating data collection. A generic and innovative circuits’ representation at the network’s input layer is proposed, encoding the devices’ dimensions, connectivity, and topological constraints. Besides, the randomness found in generative models is embedded directly into the feature vector, as the order of the features per device is shuffled in the input vector. Shuffling the order of the devices’ features in the input not only brings multi-modality but also solves a generalization problem, as there is not any natural order defined to place devices in the feature vector. As a proof of concept, a deep artificial neural network capable of proposing different placement solutions, in less than 150 ms each, for six amplifier topologies and, in multiple technology nodes ranging from 350 nm down to 65 nm, is demonstrated. DeepPlacer was capable of producing correct solutions for topologies and technology nodes not present in the training set, showing good generalization while not hindering circuit performance due to the placement.

A Semiphysical Semibehavioral Analytical Model for Switching Transient Process of SiC MOSFET Module

A semiphysical semibehavioral analytical model for switching transient of silicon carbide (SiC) MOSFET power module is proposed in this article. The model is developed for the applications in design automation where the tradeoff between accuracy and efficiency is important. The estimation of switching losses and voltage/current overshoots is mainly concerned in the proposed model. The switching transient is divided into subperiods according to the equivalent circuit of SiC MOSFET and the approximate physical mechanism during the process. The influence of the opposite device in the half-bridge is included in the analysis and corresponding derivations are made. Behavioral modeling of the waveforms is used in the subperiods where the mechanisms of the transient process are very complicated. The tradeoff between accuracy and efficiency is well implemented with this modeling approach. The time consumption of the proposed model is less than 50% of those of the previous analytical models and the accuracy is also acceptable. The errors on overshoots are less than 10% on average and the errors on switching losses are around 10%-20%. Experiment results are given and the effectiveness of the proposed model is proven.

Reverse Engineered Design Automation: Applying Knowledge Based Engineering Techniques to a Case of Automotive Fixtures Design Configuration

AbstractIn the production of automotive body components, fixtures are an important part of the ongoing work on geometrical assurance. The fixture is uniquely defined for each component, and the design and configuration of these are time-consuming and takes a lot of effort. The objective with this paper is to explore the use of a design automation approach and application to semi-automate the configuration process of the fixture product. The paper presents an approach to automate the configuration of the fixtures in a flexible way, by reverse engineering the configuration of the fixture product from a generic blueprint that represents the expected outcome of the process, using a knowledge-based engineering approach applied to a computer aided design (CAD) environment. A reverse-engineered design automation toolbox for a CAD-software is developed. The toolbox is developed to lead a user through the configuration process, in the way that the experts want it done, end-to-end, making use of some unconventional solutions from a design automation perspective.

Estimating the Impact of Design Automation: The Influence of Knowledge on Potential Estimation

AbstractAssessing the impact of design automation on design practice prior to its implementation is difficult and subject to uncertainties. One reason for this is the designers' lack of knowledge about design automation. In this work, an industrial case study focusing on conceptual design of hydraulic circuits is conducted to assess the impact of the designers' knowledge on design automation potential estimation. In particular, the impact of demonstrating a prototypical implementation of a design automation application is investigated as a means to enhance the designers' knowledge about design automation. In this respect, a given set of metrics is rated twice to enable a comparative study: prior to and after introducing the design automation prototype. The yielded results show that the knowledge impacts the rating and supports reliability of potential estimation. Further, it is shown that designers acknowledge design automation potential for the early stages of design given sufficient knowledge about design automation. Yet, the results also indicate that careful attention needs to be put on the aspects covered by the prototype in order to avoid biasing participants.

Task categorisation for identification of design automation opportunities

ABSTRACTEngineering design automation has been an active field of research and application for more than five decades. Despite a multitude of available methods stemming from research fields such as Knowledge-Based Engineering (KBE) and Computational Design Synthesis (CDS) the application context in industry is mostly limited to routine tasks. Here we propose a means to foster the transition of academic methods to industrial practice through a comprehensible and comprehensive design automation task categorisation that allows practitioners to grasp the opportunities state-of-the-art design automation offers. The categorisation is based on a critical investigation of 77 papers stemming from KBE and CDS, respectively, and is detailed with respect to knowledge needed for complete formalisation of a task, i.e. inputs, outputs and goals, as well as available automation methods. A thorough discussion indicates the context of the work with current design practice and provides a consolidation of the research fields KBE and CDS including the derivation of technological requirements for design automation task definition by practitioners. Thus, this paper contributes not only by consolidating two research fields but also by presenting technological requirements for further streamlining the process of realising design automation applications in industry.

Fast Broadband Modeling of Traces Connecting Vias in Printed Circuit Boards Using Broadband Green’s Function Method

In this paper, the broadband Green’s function with low wavenumber extraction (BBGFL) is applied to modeling of traces connecting vias in arbitrarily shaped power/ground planes of printed circuit boards (PCBs). The proposed modeling method is a hybrid technique based on mode decomposition: BBGFL is used to fast compute the vias in power/ground planes, MoM is used to calculate the impedance matrix of the traces, and a physical circuit model is then applied to combine the vias and traces in the power/ground planes. The present method is compared to the method of moments (MoM) and the commercial tool HFSS. Results show that the results of the present technique are in good agreement with MoM and HFSS on the radiated emissions from PCBs. BBGFL is several hundred times faster than HFSS in CPU time for broadband simulations. The technique provides a fast broadband solution for system-level modeling of high-speed interconnects with vias and traces in electronic design automation design and applications.

Boolean Satisfiability Solvers and Their Applications in Model Checking

Boolean satisfiability (SAT)—the problem of determining whether there exists an assignment satisfying a given Boolean formula—is a fundamental intractable problem in computer science. SAT has many applications in electronic design automation (EDA), notably in synthesis and verification. Consequently, SAT has received much attention from the EDA community, who developed algorithms that have had a significant impact on the performance of SAT solvers. EDA researchers introduced techniques such as conflict-driven clause learning, novel branching heuristics, and efficient unit propagation. These techniques form the basis of all modern SAT solvers. Using these ideas, contemporary SAT solvers can often handle practical instances with millions of variables and constraints. The continuing advances of SAT solvers are the driving force of modern model checking tools, which are used to check the correctness of hardware designs. Contemporary automated verification techniques such as bounded model checking, proof-based abstraction, interpolation-based model checking, and IC3 have in common that they are all based on SAT solvers and their extensions. In this paper, we trace the most important contributions made to modern SAT solvers by the EDA community, and discuss applications of SAT in hardware model checking.

A DC current–voltage model for organic thin film transistor for circuit design

Organic integrated circuits based on organic thin film transistors (OTFT) are gaining more and more attention nowadays, the availability of accurate spice-like device model for OTFTs suitable for Electronic design automation (EDA) applications is particularly attractive. In this paper, we demonstrate the applicability of the accurate direct-current (DC) model for OTFTs suitable for EDA, the parameters in the unified model all can be extracted in a simple and direct way from the experimental measurements. Two types of top source and drain contact (TC) pentacene TFTs with different gate dielectrics are researched on, simulation results based Simulation Program with Integrated Circuit Emphasis (SPICE) are obtained with this model and parameters extracted, which show a very good agreement with measured curves in both transfer and output characteristics, so the DC model and the extracted parameters are verified.

Adaptable methodology for automation application development

An adaptable methodology for automation application development (AMAAD) is introduced. This development methodology is based on the key concept that design automation (DA) applications are a subset of higher level knowledge-based engineering (KBE) applications, and thus can be developed using a subset of KBE methods. The proposed methodology is largely built upon two existing KBE methodologies: CommonKADS and MOKA, which have become popular models for automating engineering processes. The proposed extension of these methods introduces flexibility to tailor the process for producing automation software to the specific needs of the problem through the specification of a number of attributes. These attributes are linked to subtasks in the key lifecycle phases of application development. This proposed methodology provides a link between KBE and DA applications and provides structure to the application development process. A software tool was written to facilitate the process of identifying the capability needs of an automated solution, and providing detail of the tasks to be followed for its development.

Why Care About PLM?

This article studies the role of product lifecycle management (PLM) in industrial engineering. The basic concepts of PLM—product data management, engineering change management, and product structure management—were also discussed. PLM provides data and management capabilities to reduce the non-value-added tasks required of engineers. It also increases engineering productivity, provides insight into engineering efforts, and improves product quality and customer satisfaction. Companies are receiving significant value and return from their PLM investments. Many companies begin implementing PLM by establishing a single source of product data, or product record. Most PLM solutions offer sophisticated interfaces to many design automation and office applications, which reduce the need to capture, store, and validate product data. Product designs are maintained as assemblies and parts in the PLM system, and that arrangement allows engineers easy searching when they are looking, for example, for legacy components, with software providing a critical control and value portion of the product. With PLM, disparate engineering teams work more collaboratively.

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.

An ant colony algorithm for minimum unsatisfiable core extraction

Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware. Furthermore, a minimum explanation of infeasibility that excludes all irrelevant information is generally of interest. A smallest-cardinality unsatisfiable subset called a minimum unsatisfiable core can provide a succinct explanation of infeasibility and is valuable for applications. However, little attention has been concentrated on extraction of minimum unsatisfiable core. In this paper, the relationship between maximal satisfiability and minimum unsatisfiability is presented and proved, then an efficient ant colony algorithm is proposed to derive an exact or nearly exact minimum unsatisfiable core based on the relationship. Finally, experimental results on practical benchmarks compared with the best known approach are reported, and the results show that the ant colony algorithm strongly outperforms the best previous algorithm.

Boosting SAT Solver Performance via a New Hybrid Approach1

Due to the widespread demands for efficient SAT solvers in Electronic Design Automation applications, methods to boost the performance of the SAT solver are highly desired. We propose a Hybrid Solution to boost SAT solver performance in this paper, via an integration of local and DPLL-based search approaches. A local search is used to identify a subset of clauses from the original formula to be passed to a DPLL SAT solver incrementally until all the clauses have been passed. In addition, the solution obtained by the DPLL solver on the subset of clauses is fed back to the local search solver to jump over any locally optimal points. The proposed solution is highly portable to the existing SAT solvers. For satisfiable instances, up to an order of magnitude speedup was obtained via the proposed hybrid solver. For unsatisfiable instances, the speedup was smaller due to the overhead.

Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite

The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partial use of benchmark suites by researchers, due to simulation time constraints, compiler difficulties, or library or system call issues is likely to happen; but a random subset can lead to misleading results. This paper analyzes the SPEC CPU2006 benchmarks using performance counter based experimentation from several state of the art systems, and uses statistical techniques such as principal component analysis and clustering to draw inferences on the similarity of the benchmarks and the redundancy in the suite and arrive at meaningful subsets. The SPEC CPU2006 benchmark suite contains several programs from areas such as artificial intelligence and includes none from the electronic design automation (EDA) application area. Hence there is a concern on the application balance in the suite. An analysis from the perspective of fundamental program characteristics shows that the included programs offer characteristics broader than the EDA programs' space. A subset of 6 integer programs and 8 floating point programs can yield most of the information from the entire suite.

A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation

A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation

Minimum-congestion hypergraph embedding in a cycle

The minimum-congestion hypergraph embedding in a cycle (MCHEC) problem is to embed the n edges in an m-vertex hypergraph as paths in a cycle on the same number of vertices, such that congestion-the maximum number of paths that use any single edge in the cycle-is minimized. The MCHEC problem has applications in electronic design automation and parallel computing. In this paper, it is proven that the MCHEC problem is NP-complete. An O((nm)/sup k+1/) algorithm is described that computes an embedding with congestion k or determines that such an embedding does not exist. Finally, a linear-time approximation algorithm for arbitrary instances is presented that computes an embedding whose congestion is at most three times optimal.

Optimal and approximate bottleneck Steiner trees

Given a set of terminals in the plane, a bottleneck Steiner tree is a tree interconnecting the terminals, in which the length of the longest edge is minimized. The bottleneck Steiner tree problem, or special cases thereof, has applications in facility location and electronic physical design automation. In this paper, we first consider algorithms for computing optimal bottleneck Steiner trees. For a given topology, we give a direct, geometric algorithm that computes an optimal rectilinear bottleneck Steiner tree in O( n 2) time, which improves on the time complexity of previous algorithms. We also give a linear-time algorithm that, given the output from the previous algorithm, computes a rectilinear Steiner tree with minimum bottleneck length and that, among all trees with minimum bottleneck length, has minimum total length. These topology-specific algorithms provide solutions to many facility location applications, and in combination with a topology enumeration algorithm, can be used to solve the more general problems that arise in other applications. We also describe some difficulties in generalizing these results to the Euclidean problem, and give a simple approximation algorithm for the Euclidean problem. We then consider computation of approximate bottleneck Steiner trees. Specifically, we derive the exact value of the bottleneck Steiner ratio in any distance metric. The bottleneck Steiner ratio is the maximum ratio of the length of the longest edge in a minimum spanning tree to the length of the longest edge in an optimal bottleneck Steiner tree. Thus, the bottleneck Steiner ratio indicates the quality of a minimum spanning tree as an approximation of an optimal bottleneck Steiner tree.