Application Specific Integrated Circuit Solution Research Articles

Special Topic on Exploratory Devices and Circuits for Compute-in-Memory

Deep learning and nonconvex optimization problems are well known data-intensive applications. Although graphic processing units (GPUs) have become the mainstream platform to accelerate the algorithms in the cloud, there is a growing interest to develop application-specific integrated-circuit (ASIC) chips for further improving the energy-efficiency for these data-intensive workloads. Digital multiply-and-accumulate (MAC) arrays are generally employed as ASIC solutions, and data flow is often optimized to increase the data reuse on-chip. Nevertheless, most of the inputs and outputs are moved across MAC arrays and from global buffers. Therefore, it is more attractive to embed the MAC computations into the memory array itself, namely compute-in-memory (CIM), to minimize the data transfer. In CIM, the vector–matrix multiplication is executed in parallel (with analog computation) where the input vectors activate multiple rows. The dot-product is obtained as the multiplication of input voltage and cell conductance, and the partial sum is added up by the column current. An analog-to-digital converter (ADC) at the edge of the array generally converts the partial sum to binary bits for further digital processing.

Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing

The flexibility and programmability of an application-specific instruction-set processor (ASIP) come at the expense of reduced area and energy efficiency compared to application-specific integrated circuit (ASIC) solutions. Nevertheless, ASIPs are desirable for versatile application domains like wireless communications and software defined radio (SDR). Typically, ASIP designers reduce the ASIC-ASIP efficiency gap by increasingly complex architectures with decreasing flexibility and usability. This paper takes the opposite approach and presents concepts for a highly efficient, lightweight SDR ASIP. Efficiency enablers include simple but effective measures like a carefully chosen instruction set, optimized data access techniques for efficient utilization of functional units, and the use of flexible floating-point arithmetic with runtime-adaptive numerical precision. We present a conceptual processor core to show the impact of these measures and discuss its potential as well as limitations compared to tailored ASIC solutions. For demonstration, we choose the field of linear multiple-input multiple-output (MIMO) detection. We present synthesis results for several design versions in 90 nm CMOS technology and the corresponding energy benchmarks. Also, we show post-layout results for a selected design to demonstrate the feasibility of our concept.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

SummaryThis paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi‐input multi‐output (MIMO) piecewise‐affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90‐nm complementary metal‐oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high‐performance and minimum unitary cost are required. Copyright © 2015 John Wiley & Sons, Ltd.

Understanding sources of ineffciency in general-purpose chips

Scaling the performance of a power limited processor requires decreasing the energy expended per instruction executed, since energy/op * op/second is power. To better understand what improvement in processor efficiency is possible, and what must be done to capture it, we quantify the sources of the performance and energy overheads of a 720p HD H.264 encoder running on a general-purpose four-processor CMP system. The initial overheads are large: the CMP was 500 x less energy efficient than an Application Specific Integrated Circuit (ASIC) doing the same job. We explore methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding. Broadly applicable optimizations like single instruction, multiple data (SIMD) units improve CMP performance by 14 x and energy by 10x, which is still 50x worse than an ASIC. The problem is that the basic operation costs in H.264 are so small that even with a SIMD unit doing over 10 ops per cycle, 90% of the energy is still overhead. Achieving ASIC-like performance and effciency requires algorithm-specifc optimizations. For each subalgorithm of H.264, we create a large, specialized functional/storage unit capable of executing hundreds of operations per instruction. This improves energy effciency by 160x (instead of 10x), and the final customized CMP reaches the same performance and within 3x of an ASIC solution's energy in comparable area.

The design of dynamically reconfigurable datapath coprocessors

Increasing nonrecurring engineering and mask costs are making it harder to turn to hardwired application specific integrated circuit (ASIC) solutions for high-performance applications. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium-volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable field programmable gate arrays to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space---a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating coprocessor. This datapath consists of hardwired function units and reconfigurable interconnect. We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application-specific platforms.

Production testing issues for ASICs for high energy physics

Many high-energy physics experiments require a large number of channels in a small volume. The use of custom or Application Specific Integrated Circuits (ASICs) in the front ends is very popular and in many cases an absolute necessity. The tools to design ASICs are readily available and wafers can be processed at moderate costs. However, very few, if any, vendors will provide tested die or chips at a reasonable cost in the low quantities (few thousand to few tens of thousands) that most experiments require. This talk will discuss the cost of testing vs. not testing of ASICs as well as ASIC testing strategies and solutions for relatively small quantities of ASICs. Specifics of the solution used by the KTeV experiment at Fermilab and the low-cost test system developed for this need will be discussed.

A New VLSI Implementation of Additive Synthesis

Additive sine-wave synthesis is one of the most powerful techniques available for sound generation. Its theoretical background dates back to the 19th century and the work of Frangois M. C. Fourier. Although any sound can be generated by the summation of an appropriate number of sine waves, the realization of complex real-time additive synthesis systems is difficult because of the large number of independent oscillators needed. Our first attempts to obtain a digital additive synthesis were carried out in the early 1970s with the TAU2 system (Bertini, Chimenti, and Denoth 1976), which consisted of a set of analog oscillators digitally controlled by a computer. The system's performance was meager by today's standards, but back then it was considered an interesting experiment that showed the power of such synthesis systems (Blum 1979). It is generally accepted that 30-100 partials are needed to generate an excellent sound, depending on the timbral characteristics (Moorer, Grey, Nad, and Strawn 1977; Comerford 1993), so it is evident that a polyphonic multitimbral synthesis will need several thousand sinusoids. The computational power required is huge, so that tens or even hundreds of powerful digital signal processors (DSPs) are needed if traditional methods are used. As a result, this technique is not widespread except in academic study, where it is studied in terms of analysis/decomposition/resynthesis (George and Smith 1992). In fact, working in the frequency domain, additive synthesis allows the management of sound characteristics in a direct and powerful way, which is attractive for the synthesis of new timbres or the modification and re-editing of existing ones. To make additive synthesis more affordable, it is strongly advisable to create an ad hoc structure, for example, an application-specific integrated circuit (ASIC) (Rodet 1996). This article describes a very large-scale integration (VLSI) implementation of additive synthesis by means of a novel system architecture that makes possible the realization of powerful ASIC solutions; the chip described permits the generation of 1,200 sinusoids in real time. The article reviews the vari-