Application-specific Hardware Research Articles

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow for SOM when implemented in software. In such cases, an application-specific hardware SOM accelerator is highly desirable. Field-programmable gate array (FPGA) implementation is a popular platform to implement hardware SOM. In our previous work, a nested hardware SOM architecture, which has a homogeneous modular structure to enhance expandability, was proposed. This paper investigates the impact of the nested hardware SOM on FPGA implementation tools that perform logic synthesis, place, and route (PAR). Experiments revealed that the nested architecture provided better results in resource usage and performance. FPGA resource usage of the nested architecture was 97.2% of that of the flat design on average. Importantly, the nested architecture operated at 10% higher clock frequencies compared to flat SOM designs. In addition, the pipeline computation was improved by increasing the pipeline stages so that it operates with a higher clock frequency. The operable clock frequency was 81 MHz, which was 21 MHz higher than its predecessor.

Edge Computing on IoT for Machine Signal Processing and Fault Diagnosis: A Review

Edge computing is an emerging paradigm that offloads the computations and analytics workloads onto the internet of things (IoT) edge devices to accelerate the computation efficiency, reduce the channel occupation of signal transmission, and reduce the storage and computation workloads on the cloud servers. These distinct merits make it a promising tool for IoT-based machine signal processing and fault diagnosis. This article reviews the edge computing methods in signal processing-based machine fault diagnosis from the aspects of concepts, state-of-the-art methods, case studies, and research prospects. In particular, the light-weight designed algorithms and application-specific hardware platforms of edge computing in the typical fault diagnosis procedures including signal acquisition, signal preprocessing, feature extraction, and pattern recognition are reviewed and discussed in detail. The review provides an insight into the edge computing framework, methods, and applications, so as to meet the requirements of IoT-based machine real-time signal processing, low-latency fault diagnosis, and high-efficient predictive maintenances.

Integrated Photonic Tensor Processing Unit for a Matrix Multiply: A Review

The explosion of artificial intelligence and machine-learning algorithms, connected to the exponential growth of the exchanged data, is driving a search for novel application-specific hardware accelerators. Among the many, the photonics field appears to be in the perfect spotlight for this global data explosion, thanks to its almost infinite bandwidth capacity associated with limited energy consumption. In this review, we will overview the major advantages that photonics has over electronics for hardware accelerators, followed by a comparison between the major architectures implemented on Photonics Integrated Circuits (PIC) for both the linear and nonlinear parts of Neural Networks. By the end, we will highlight the main driving forces for the next generation of photonic accelerators, as well as the main limits that must be overcome.

Deep Learning Inferencing with High-performance Hardware Accelerators

As computer architectures continue to integrate application-specific hardware, it is critical to understand the relative performance of devices for maximum app acceleration. The goal of benchmarking suites, such as MLPerf for analyzing machine learning (ML) hardware performance, is to standardize a fair comparison of different hardware architectures. However, there are many apps that are not well represented by these standards that require different workloads, such as ML models and datasets, to achieve similar goals. Additionally, many apps, like real-time video processing, are focused on latency of computations rather than strictly on throughput. This research analyzes multiple compute architectures that feature ML-specific hardware on a case study of handwritten Chinese character recognition. Specifically, AlexNet and a custom version of GoogLeNet are benchmarked in terms of their streaming latency and maximum throughput for optical character recognition. Considering that these models are composed of fundamental neural network operations yet architecturally different from each other, these models can stress devices in different yet insightful ways that generalizations of the performance of other models can be drawn from. Many devices featuring ML-specific hardware and optimizations are analyzed including Intel and AMD CPUs, Xilinx and Intel FPGAs, NVIDIA GPUs, and Google TPUs. Overall, ML-oriented hardware added to the Intel Xeon CPUs helps to boost throughput by 3.7× and to reduce latency by up to 34.7×, which makes the latency of Intel Xeon CPUs competitive on more parallel models. The TPU devices were limited in terms of throughput due to large data transfer times and not competitive in terms of latency. The FPGA frameworks showcase the lowest latency on the Xilinx Alveo U200 FPGA achieving 0.48 ms on AlexNet using Mipsology Zebra and 0.39 ms on GoogLeNet using Vitis-AI. Through their custom acceleration datapaths coupled with high-performance SRAM, the FPGAs are able to keep critical model data closer to processing elements for lower latency. The massively parallel and high-memory GPU devices with Tensor Core accelerators achieve the best throughput. The NVIDIA Tesla A100 GPU showcases the highest throughput at 42,513 and 52,484 images/second for AlexNet and GoogLeNet, respectively. 1

Surface-Mount Zero-Ohm Jumper Resistor Characterization in High-Speed Controlled Impedance Transmission Lines.

Zero-ohm resistors, also known as jumpers, are commonly used in early radio frequency (RF) prototypes as they can help engineers identify the most optimal engineering solution for their system or create application-specific hardware configurations in products. One of the key considerations when using zero-ohm jumpers in RF circuits is the potential for signal loss and interference. Every circuit connection creates a small amount of resistance and impedance, eventually adding up over long distances or in complex circuits. This paper proposes a quantitative characterization summary of standard 0201-, 0402-, 0603-, and 0805-size surface-mount package jumpers, as well as lead-free and lead solder wires, in high-frequency applications by means of time domain reflectometry (TDR) and S-parameter measurements. The typical offset from the target 50 Ω impedance was measured to be around 3 Ω, or 5.8% relative to the measured reference value. According to S-parameter measurement results, no visible impact on attenuation was spotted up to 5 GHz compared to the reference S21 curve.

Modular Hardware/Software Architecture for Edge Units in Highly Flexible Manufacturing Systems

With the increasing demand for individualized production and swift adaptability to changing market needs, new manufacturing system concepts emerge. Aiming for high flexibility and scalability, they rely on universal reconfigurable machines that can be used in various production steps by automatically changing tools and sensors. Consequently, the data processing infrastructure is required to support the frequent exchange of process-specific software applications, ranging from control and monitoring tasks to complex sensor data processing. This can be a major challenge when computation-intensive software is supported by hardware acceleration to achieve the desired performance or latency requirements. In this paper, we present an edge unit architecture that allows for hosting such applications while meeting the needs for modularity and reconfigurability. It builds upon a hypervisor to partition fixed processing resources among the applications. We present a mechanism that extends this partitioning to field-programmable gate arrays (FPGA) by using dynamic partial reconfiguration. This provides the option to deploy application-specific hardware accelerators with computation-intensive applications while maintaining modularity and on-line reconfigurability. We conclude the paper by pointing out the potential of the proposed architecture based on a use case for automated disassembly in a reconfigurable robotic cell.

Sorting in Memristive Memory

Sorting data is needed in many application domains. Traditionally, the data is read from memory and sent to a general-purpose processor or application-specific hardware for sorting. The sorted data is then written back to the memory. Reading/writing data from/to memory and transferring data between memory and processing unit incur significant latency and energy overhead. In this work, we develop the first architectures for in-memory sorting of data to the best of our knowledge. We propose two architectures. The first architecture is applicable to the conventional format of representing data, i.e., weighted binary radix. The second architecture is proposed for developing unary processing systems, where data is encoded as uniform unary bit-streams. As we present, each of the two architectures has different advantages and disadvantages, making one or the other more suitable for a specific application. However, the common property of both is a significant reduction in the processing time compared to prior sorting designs. Our evaluations show on average 37 × and 138× energy reduction for binary and unary designs, respectively, compared to conventional CMOS off-memory sorting systems in a 45 nm technology. We designed a 3×3 and a 5×5 Median filter using the proposed sorting solutions, which we used for processing 64×64 pixel images. Our results show a reduction of 14× and 634× in energy and latency, respectively, with the proposed binary, and 5.6× and 152×10 3 in energy and latency with the proposed unary approach compared to those of the off-memory binary and unary designs for the 3 × 3 Median filtering system.

A System-on-Chip Based Hybrid Neuromorphic Compute Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks.

Despite the great strides neuroscience has made in recent decades, the underlying principles of brain function remain largely unknown. Advancing the field strongly depends on the ability to study large-scale neural networks and perform complex simulations. In this context, simulations in hyper-real-time are of high interest, as they would enable both comprehensive parameter scans and the study of slow processes, such as learning and long-term memory. Not even the fastest supercomputer available today is able to meet the challenge of accurate and reproducible simulation with hyper-real acceleration. The development of novel neuromorphic computer architectures holds out promise, but the high costs and long development cycles for application-specific hardware solutions makes it difficult to keep pace with the rapid developments in neuroscience. However, advances in System-on-Chip (SoC) device technology and tools are now providing interesting new design possibilities for application-specific implementations. Here, we present a novel hybrid software-hardware architecture approach for a neuromorphic compute node intended to work in a multi-node cluster configuration. The node design builds on the Xilinx Zynq-7000 SoC device architecture that combines a powerful programmable logic gate array (FPGA) and a dual-core ARM Cortex-A9 processor extension on a single chip. Our proposed architecture makes use of both and takes advantage of their tight coupling. We show that available SoC device technology can be used to build smaller neuromorphic computing clusters that enable hyper-real-time simulation of networks consisting of tens of thousands of neurons, and are thus capable of meeting the high demands for modeling and simulation in neuroscience.

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems

Embedded systems continue to rapidly proliferate in diverse fields, including medical devices, autonomous vehicles, and more generally, the Internet of Things (IoT). Many embedded systems require application-specific hardware components to meet precise timing requirements within limited resource (area and energy) constraints. High-level synthesis (HLS) is an increasingly popular approach for improving the productivity of designing hardware and reducing the time/cost by using high-level languages to specify computational functionality and automatically generate hardware implementations. However, current HLS methods provide limited or no support to incorporate or utilize precise timing specifications within the synthesis and optimization process. In this paper, we present a hybrid high-level synthesis (H-HLS) framework that integrates state-based high-level synthesis (SB-HLS) with performance-driven high-level synthesis (PD-HLS) methods to enable the design and optimization of application-specific embedded systems in which timing information is explicitly and precisely defined in state-based system models. We demonstrate the results achieved by this H-HLS approach using case studies including a wearable pregnancy monitoring device, an ECG-based biometric authentication system, and a synthetic system, and compare the design space exploration results using two PD-HLS tools to show how H-HLS can provide low energy and area under timing constraints. © 2021 Elsevier Science. All rights reserved

An efficient hardware architecture based on an ensemble of deep learning models for COVID -19 prediction.

Deep learning models demonstrate superior performance in image classification problems. COVID-19 image classification is developed using single deep learning models. In this paper, an efficient hardware architecture based on an ensemble deep learning model is built to identify the COVID-19 using chest X-ray (CXR) records. Five deep learning models namely ResNet, fitness, IRCNN (Inception Recurrent Convolutional Neural Network), effectiveness, and Fitnet are ensembled for fine-tuning and enhancing the performance of the COVID-19 identification; these models are chosen as they individually perform better in other applications. Experimental analysis shows that the accuracy, precision, recall, and F1 for COVID-19 detection are 0.99,0.98,0.98, and 0.98 respectively. An application-specific hardware architecture incorporates the pipeline, parallel processing, reusability of computational resources by carefully exploiting the data flow and resource availability. The processing element (PE) and the CNN architecture are modeled using Verilog, simulated, and synthesized using cadence with Taiwan Semiconductor Manufacturing Co Ltd (TSMC) 90 nm tech file. The simulated results show a 40% reduction in the latency and number of clock cycles. The computations and power consumptions are minimized by designing the PE as a data-aware unit. Thus, the proposed architecture is best suited for Covid-19 prediction and diagnosis.

Formal verification of high-level synthesis

High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

Evaluation of Green Alternatives for Blockchain Proof-of-Work (PoW) Approach

Following the footprints of Bitcoins, many other cryptocurrencies were developed mostly adopting the same or similar Proof-of-Work (PoW) approach. Since completing the PoW puzzle requires extremely high computing power, consuming a vast amount of electricity, PoW has been strongly criticised for its antithetic stand against the notion of green computing. Use of application-specific hardware, particularly application-specific integrated circuits (ASICs) has further fuelled the debate, as these devices are of no use once they become “legacy” and hence obsolete to compete in the mining race, thus contributing to electronics waste. Therefore, this paper surveys the currently available alternative approaches to PoW and evaluates their applicability - especially their appropriateness in terms of greenness.

An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications

The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server computing capacity, and the security issues that occur in the data communication process. However, edge-based IoT systems performance was insufficient to process large numbers of data due to limited power supply, fixed hardware functions, and limited hardware resources. To improve their performance, application-specific hardware can be installed in edge devices, but performance cannot be improved except for specific applications due to a fixed function of an application-specific hardware. This paper introduces an edge-centric metamorphic IoT (mIoT) platform that can use various hardware modules through on-demand partial reconfiguration, despite the limited hardware resources of edge devices. In addition, this paper introduces an RISC-V based metamorphic IoT processor (mIoTP) with reconfigurable peripheral modules. We experimented to prove that the proposed structure can reduce the server access of edges and can be applied to a large-scale IoT system. Experiments were conducted in a single-edge environment and a large-scale environment combining one physical edge and 99 virtual edges. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration prediction algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to our previous study in which the prediction process was executed at the server. Furthermore, we confirmed that there is no additional reconfiguration time overhead even for the large IoT systems.

A Binary Translation Framework for Automated Hardware Generation

As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

Memory-Augmented Neural Networks on FPGA for Real-Time and Energy-Efficient Question Answering

Memory-augmented neural networks (MANNs) were introduced to handle long-term dependent data efficiently. MANNs have shown promising results in question answering (QA) tasks that require holding contexts for answering a given question. As demands for QA on edge devices have increased, the utilization of MANNs in resource-constrained environments has become important. To achieve fast and energy-efficient inference of MANNs, we can exploit application-specific hardware accelerators on field-programmable gate arrays (FPGAs). Although several accelerators for conventional deep neural networks have been designed, it is difficult to efficiently utilize the accelerators with MANNs due to different requirements. In addition, characteristics of QA tasks should be considered for further improving the efficiency of inference on the accelerators. To address the aforementioned issues, we propose an inference accelerator of MANNs on FPGA. To fully utilize the proposed accelerator, we introduce fast inference methods considering the features of QA tasks. To evaluate our proposed approach, we implemented the proposed architecture on an FPGA and measured the execution time and energy consumption for the bAbI data set. According to our thorough experiments, the proposed methods improved speed and energy efficiency of the inference of MANNs up to about 25.6 and 28.4 times, respectively, compared with those of CPU.

Designing a GPU-parallel algorithm for raw SAR data compression: A focus on parallel performance estimation

When a Synthetic Aperture Radar (SAR) acquires raw data using a satellite or airborne platform, it must be transferred to the ground for further processing. For example, SAR raw data need a so-called ’focusing’ signal processing to render it into a visible image. Such processing is time and computing consuming, and it is commonly carried out in computing centres. Since the data transfer rate is a typical limitation when communicating with the ground station, compression is necessary to reduce transmission time. So far, this procedure has been implemented in application-specific hardware, but recent adoption of avionic computational GPUs opened to new high-performance onboard perspectives. Due to the limited availability of avionic GPUs, we focused on parallel performance estimation starting from measures relative to a similar off-the-shelf solution. In this paper, we present a GPU algorithm for raw SAR data compression, which uses 1-dimensional DCT transforms, followed by quantisation and entropy coding. We evaluate results using ENVISAT (Environmental Satellite) ASAR Image Mode level 0 data by measuring compression rates, statistical parameters, and distortion on decompressed and then focused images. Moreover, by evaluating the Algorithmic Overhead induced by the parallelisation strategy, we predict the best thread-block configuration for possible adoption of such a GPU algorithm on one of the most available avionic hardware.

Predictive Analysis of IoT Enabled Garden Soil Requirements using Web Services

Smart gardening plays a key role in both supply and distribution of water to the plants. Plants play a key role in providing habitat and food for wild animals, human beings and regulate the water cycle. The important parameters for the quality and productivity of a plant growth are soil temperature, soil moisture, nutrients, humidity and Potential of Hydrogen (PH). Soil moisture is the main factor which is most the effective reliable way to increase yielding. The main aim of the present research work, is to sense the essentials and fulfil the needs of the plants. For the real time practice there are five different garden zones such as Patio, Front yard, Back yard, Balcony and Terrace. Switch is used to operate the solenoid valve which is instructed by the web server in communication with the cloud data base. By physical verification and plant requirements a time interval of 4 min was set in the cloud data base. Internet of things (IOT) and cloud computing are two complementary technologies which were merged with the application specific hardware design enriched with smart sensors collectively provides the data which is stored in cloud. The data stored in the cloud database is accessed using the web services. Feedback system which is used to send and receive the data that can be used for the analysis of requirements

Heuristic recurrent algorithms for photonic Ising machines

The inability of conventional electronic architectures to efficiently solve large combinatorial problems motivates the development of novel computational hardware. There has been much effort toward developing application-specific hardware across many different fields of engineering, such as integrated circuits, memristors, and photonics. However, unleashing the potential of such architectures requires the development of algorithms which optimally exploit their fundamental properties. Here, we present the Photonic Recurrent Ising Sampler (PRIS), a heuristic method tailored for parallel architectures allowing fast and efficient sampling from distributions of arbitrary Ising problems. Since the PRIS relies on vector-to-fixed matrix multiplications, we suggest the implementation of the PRIS in photonic parallel networks, which realize these operations at an unprecedented speed. The PRIS provides sample solutions to the ground state of Ising models, by converging in probability to their associated Gibbs distribution. The PRIS also relies on intrinsic dynamic noise and eigenvalue dropout to find ground states more efficiently. Our work suggests speedups in heuristic methods via photonic implementations of the PRIS.

CORDIC-Astrocyte: Tripartite Glutamate-IP3-Ca 2+ Interaction Dynamics on FPGA.

Real-time, large-scale simulation of biological systems is challenging due to different types of nonlinear functions describing biochemical reactions in the cells. The promise of the high speed, cost effectiveness, and power efficiency in addition to parallel processing has made application-specific hardware an attractive simulation platform. This paper proposes high-speed and low-cost digital hardware to emulate a biological-plausible astrocyte and glutamate-release mechanism. The nonlinear terms of these models were calculated using a high-precision and cost-effective algorithm. Subsequently, the modified models were simulated to study and validate their functions. We developed several hardware versions by setting different constraints to investigate trade-offs and find the best possible design. FPGA implementation results confirmed the ability of the design to emulate biological cell behaviours in detail with high accuracy. As for performance, the proposed design turned out to be faster and more efficient than previously published works that targeted digital hardware for biological-plausible astrocytes.

FPGA-Based Pipelined Architecture for Real-Time Estimation of Sensitivity Maps Using Pre-Scan Method in Parallel MRI

Parallel MRI (pMRI) is a widely used technique for increasing the MRI acquisition speed, by using multiple receiver coils with spatially discriminated sensitivities. Sensitivity encoding (SENSE) is a parallel MRI technique used for reconstructing the aliasing free images from the under-sampled MRI data using the spatial information obtained from multiple receiver coils. Precise receiver coil sensitivity estimation is critical for the correct image reconstruction from the under-sampled data in SENSE. Pre-scan method is a quick and conventionally used method for correct estimation of the receiver coil sensitivities, to be used in SENSE. In this work, an application-specific hardware implemented on FPGA (Field Programmable Gate Array) for real-time sensitivity maps estimation using the pre-scan method is proposed. The proposed architecture has the potential to be installed on the receiver coil data acquisition system, which would provide sensitivity maps for image reconstruction, without moving the raw data to the MRI workstation. Parallelism is utilized in the proposed pipelined architecture to make it even faster. From the experimental results, it is shown that the proposed architecture estimates the sensitivity maps in only 1.466[Formula: see text]ms for eight receiver coils. Furthermore, high mean SNR (30[Formula: see text][Formula: see text]dB), low root-mean-square-error ([Formula: see text]) and low artifact power ([Formula: see text]) are achieved for the under-sampled human head, cardiac and phantom data sets (acceleration factor = 2), reconstructed with SENSE algorithm utilizing the sensitivity maps estimated by the proposed architecture.