Application-specific Computer Research Articles

Decompressor for hardware applications

The use of lossless compression in the application specific computers provides such advantages as minimized amount of memory, increased bandwidth of interfaces, reduced energy consumption, and improved self-testing systems. The article discusses known algorithms of lossless compression with the aim of choosing the most suitable one for implementation in a hardware-software decompressor. Among them, the Lempel-Ziv-Welch (LZW) algorithm makes it possible to perform the associative memory of the decompressor dictionary in the simplest way by using the sequential reading the symbols of the decompressed word. The analysis of the existing hardware implementations of the decompressors showed that the main goal in their development was to increase the bandwidth at the expense of increasing hardware costs and limited functionality. It is proposed to implement the LZW decompressor in a hardware module based on a microprocessor core with a specialized instruction set. For this, a processor core with a stack architecture was selected, which is developed by the authors for the tasks of the file grammar analyzing. Additional memory block for the dictionary storing and an input buffer which converts the byte stream of the packed file into a sequence of unpacked codes are added to it. The processor core instruction set is adjusted to both speed up decompression and reduce hardware costs. The decompressor is described by the Very high-speed integral circuit Hardware Description Language and is implemented in a field programable gate array (FPGA). At a clock frequency of up to two hundred megahertz, the average throughput of the decompressor is more than ten megabytes per second. Because of the hardware and software implementation, an LZW decompressor is developed, which has approximately the same hardware costs as that of the hardware decompressor and has a lower bandwidth at the costs of flexibility, multifunctionality, which is provided by the processor core software. In particular, a decompressor of the Graphic Interchange Format files is implemented on the basis of this device in FPGA for the application of dynamic visualization of patterns on the embedded system display

Image Denoising based on Deep Learning

Image denoising has always been one of the research hotspots in the field of image processing, which aims to remove the noise from the imaging device or external noise environment and other interfering factors in the image to restore the noisy image to the original clean and noise-free image. Mature algorithms and machine learning techniques have been developed previously for different application situations and specific computer vision works. Image denoising based on deep learning can adaptively learn image content and is suitable for image denoising tasks in high-noise environments. This paper builds a model based on the representative image denoising algorithm DnCNN, and discusses the performance difference with other denoising algorithms. All the results show the new methods are usually more efficient than traditional ones which can process pictures that are under more complex conditions.

MICROPROCESSOR FOR INTELLIGENT SPACE SURVEILLANCE SYSTEMS WITH SPACEWIRE/GIGASPACEWIRE/SPACEFIBRE LINKS

The article presents architecture and main features of 90 nm CMOS radiation tolerant MCDE50F ASIC as multiprocessor heterogeneous SoC (System-on-Chip) which contains MIPS64 RISC core, graphic processing unit (GPU) and application-specific computer vision Elcore50 DSP. High-speed data input/output is performed by multiprotocol SpaceFibre/GigaSpaceWire/ SpaceWire ports combined with built-in multichannel SpaceFibre/GigaSpaceWire/SpaceWire based switch. MCDE50F ASIC is intended for space “intelligent” surveillance system applications, which require high computational performance in signal and image processing, including computer vision functions support, and high-speed deliverance of massive data arrays. An example of onboard data processing system structure based on MCDE50F ASIC is presented. Performance characteristics of MCDE50F ASIC implementing OpenVX standard functions are also given.

Training, Self-Efficacy, and Performance; a Replication Study

A conceptual replication of multiple prior IS studies was conducted with the aim of providing stronger empirical support for those results. Conducting six separate longitudinal studies, the effect of professional training on improving one’s application-specific computer self-efficacy (AS-CSE) was shown. Also in line with some prior IS studies it was shown that an application-specific measure of self-efficacy is better able to predict one’s performance in accomplishing tasks in the corresponding domain than a general computer self-efficacy (GCSE) measure. Moreover, it is shown that, regardless of the type and characteristics of the training method, individuals’ perceptions of quality of training significantly affects their AS-CSE after the training course.

Surviving the end of frequency scaling with reconfigurable dataflow computing

Over the past decade x86 processors have come to dominate the world's largest supercomputers. However in the future conventional multicore processors are unlikely to be able to deliver the necessary performance per $ and per W to achieve exascale performance. Heterogeneous computing is emerging as a powerful alternative to conventional multi-core to help address these challenges. In this paper we describe our approach to Maximum Performance Computing - building applicationspecific computers which complement conventional x86 processors with high performance dataflow engines implemented on FPGA to provide 10-100x improvements in performance and performance/W. We describe the MaxCompiler programming system which allows software engineers to create dataflow engines optimized for their particular applications, and discuss an example application that has been accelerated using this methodology.

An empirical examination of factors contributing to the creation of successful e-learning environments

Although existing models of e-learning effectiveness in information systems (IS) have increased our understanding of how technology can support and enhance learning, most of our models do not take into account the importance of social presence. Thus, this study extends previous research by developing a model of e-learning effectiveness which adds social presence to other oft studied variables including application-specific computer self-efficacy (AS-CSE), perceived usefulness, course interaction, and e-learning effectiveness. Using data from 345 individuals, this model was validated through a field study in an introductory IS survey course. Results indicate that AS-CSE and perceived usefulness were related to course performance, course satisfaction, and course instrumentality. In addition, course interaction was related to course performance and satisfaction. Finally, social presence was related to course satisfaction and course instrumentality. Implications for research and practice are discussed.

An empirical investigation of sources of application-specific computer-self-efficacy and mediators of the efficacy—performance relationship

Integrating theory from research on training, computer self-efficacy (CSE), and motivation, this research validated a model of four factors that contribute to application-specific computer self-efficacy (AS-CSE) formation (previous experience, personality, learning goal orientation and computer anxiety) and three factors that mediate the relationship between AS-CSE and performance (goal level, goal commitment and performance goal orientation (PGO)). Using data from 313 individuals in an introductory computer skills course, the model was validated for database software. Results indicate that previous database software experience, trainee personality and learning goal orientation were positively related to AS-CSE, whereas computer anxiety was negatively related to AS-CSE. Additionally, goal level, goal commitment and PGOs were related to database test performance, and the relationship between AS-CSE and database test performance was also partially mediated by goal level and goal commitment. Implications for research and practice are discussed.

FPGA-based adaptive tracking estimation computer

We describe an FPGA-based adaptive tracking estimation computer (FATEC) for a multiple target tracking (MTT) radar system. Its design is centered around a small processor core customized according to the requirements of tracking application, to run the main control program and provide software flexibility, with a number of tracking algorithms (models) implemented in hardware-type functional units, in order to meet the timing requirements of the application. The FATEC approach provides combination of software flexibility, hardware efficiency, and functional adaptivity of implementation of application-specific computers for the other applications of a similar type, enabling various partitioning options between the software and the hardware parts of the solution.

Integer multiplication with overflow detection or saturation

High-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two n-bit integers are multiplied to produce a 2n-bit product. To prevent growth in word length, processors typically return the n least significant bits of the product and a flag that indicates whether or not overflow has occurred. Alternatively, some processors saturate results that overflow to the most positive or most negative representable number. This paper presents efficient methods for performing unsigned or two's complement integer multiplication with overflow detection or saturation. These methods have significantly less area and delay than conventional methods for integer multiplication with overflow detection or saturation.

Robust and Parallel Control of Industrial Processes

A new robust ratio control method using Internal Model Control (IMC) principle has been evolved. In the IMC robust control problem, the state space formulation and two-degrees-of-freedom controller as they are introduced here determine certain important parameters of the ratio control. This realisation besides being robust has parallel structure. Basic feed forward and feed back control are shown to be realised using this robust ratio control. Importance of this method for the design of application specific VISI's or direct computer implementation for online control of industrial processes has been outlined.

Optimizing throughput and resource utilization using pipelining: Transformation based approach

A simple formulation of pipelining: "Pipelining withN stages is equivalent to retiming where the number of delays on all inputs or all outputs, but not both, is increased byN" is used as the basis for a convenient and efficient treatment of pipelining in the design of application specific computers. Pipelining according to the objective function (throughput or resource utilization) and the latency is introduced. For two polynomial complexity pipelining classes, optimal algorithms are presented. For two other classes both proofs of NP-completeness and efficient probabilistic algorithms are presented. Both theoretical and experimental properties of pipelining are discussed and a relationship with other transformations is explored. Due to similar formulations for both software pipelining and the pipelining presented here, all results can be easily modified for use in compilers for general purpose computers. We have also developed a polynomial complexity algorithm for determining the iteration bound.

FASTRUN - A High Performance Computing Device for Molecular Mechanics Using a Pipeline Architecture

A deep, synchronous pipeline architecture has been selected for a computing device with a power of 500 Million floating point operations per second (MFlops). The device calculates the forces and energy due to pair-wise interactions of many objects in a system. Considerations relating to application specific high-performance computer architectures are addressed. In addition, topics specifically relating to very deep, synchronous unidirectional pipelines are discussed. A key element of the device, a quadratic interpolator based on a lookup table, has been developed and tested. Five of these interpolators with a total computing power of 280 Mflops will be employed in the device.