Application-specific Architectures Research Articles

HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learning

AbstractLinear Regression (LR), as one of the essential Machine Learning (ML) models, incurs massive data crunching during the training phase based on many data points. Considering the computationally intensive nature in the LR models, an optimized dedicated hardware IP core design can be very effective. This paper proposes the following novelties: (a) an optimized hardware IP core design of linear regression‐based machine learning model using high‐level synthesis (HLS). More specifically, independent application specific datapath architectures of hardware IP for computing optimal bias and intercepts and cost function in LR‐ML are presented here; (b) an optimized hardware IP core design of LR based ML model by deducing dependency graph from its corresponding mathematical foundation; (c) register transfer level (RTL) design, using HLS, of the optimized LR based ML hardware IP core for computing cost function; (d) linear regression IP core design using multi‐layered tree‐height transformation (THT) and swarm intelligence based architectural exploration for optimized HLS design.

IoT-Fog architectures in smart city applications: A survey

Smart cities improve the quality of life of people by utilizing the benefits of Information and communication technology (ICT) and the Internet of things (IoT). The applications of the smart city often rely on the cloud for services. No doubt cloud provides an ample amount of resources as a service but still it has limitations in terms of unreliable latency, mobility, and location awareness due to their multi-hop distance from the IoT devices. Fog computing avoids these limitations by providing services nearer to the edges. In this work we investigate the already proposed IoT-Fog based application specific smart city architectures and review them based on scalability, heterogeneity, mobility, energy conservation, latency, and security. Additionally, we discuss the applications and highlight the challenges that fog computing faces. We also present a case study of a smart city scenario with multiple applications of IoT.

A Survey on Application Specific Processor Architectures for Digital Hearing Aids

On the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors. Special attention is given to the increasingly common application-specific instruction-set processors (ASIPs). The main focus of this paper lies on hardware-related aspects such as the processor architecture, the interfaces, the application specific integrated circuit (ASIC) technology, and the operating conditions. The different hearing aid implementations are compared in terms of power consumption, silicon area, and computing performance for the algorithms used. Challenges for the design of future hearing aid processors are discussed based on current trends and developments.

Hybrid evolutionary network architecture search (HyENAS) for convolution class of deep neural networks with applications

AbstractConvolutional Neural Networks (CNNs) and its variants are increasingly used across wide domain of applications achieving high performance measures. For high performance, application specific CNN architecture is required, hence the need for network architecture search (NAS) becomes essential. This paper proposes a hybrid evolutionary approach for network architecture search (HyENAS), and targets convolution class of neural networks. One of the significant contribution of this technique is to completely evolve the high performance network by simultaneously finding network structures and their corresponding parameters. An elegant string representation has been proposed which efficiently represents the network. The concept of sparse block evolving requisite layer wise features for dense network is deployed. This permits the network to dynamically evolve for a specific application. In comparison to the other state‐of‐art methods, the high performance of the proposed HyENAS approach is demonstrated across various benchmark data sets belonging to the domain of malariology, oncology, neurology, ophthalmology, and genomics. Further, to deploy the proposed model on lower hardware specification devices, another salient feature of the HyENAS technique is to seamlessly sift out the simpler network architecture with comparable accuracy.

Obfuscated Hardware Accelerators for Image Processing Filters—Application Specific and Functionally Reconfigurable Processors

Hardware accelerators are widely used as computationally-intensive cores in consumer electronics (CE) applications. However security and speed of such hardware accelerators, that are responsible for computing data-intensive tasks, play an important role in improving consumer experience in terms of safety and performance. This article presents novel low power multi-modal hardware accelerator architectures viz. application specific processor and functionally reconfigurable processor for image processing filter of $3\times 3$ kernel matrix size. In the proposed functionally reconfigurable processor of $3\times 3$ filter, the same design can be used for five different image processing filters - blurring, sharpening, vertical embossment, horizontal embossment and Laplace edge detection, by varying control input. Further, application specific processor designs of these five types of $3\times 3$ filters are also presented in this article. Additionally, application specific processor architecture of $5\times 5$ filter kernel matrix size is also reported in this article. The results confirm that the proposed hardware accelerators achieve strong security and low design cost.

An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF[Formula: see text]. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF[Formula: see text]. It is found through experimental results that an ASIF[Formula: see text] is 4–9[Formula: see text] area-efficient and requires [Formula: see text] lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53[Formula: see text] area saving as compared to a traditional FPGA.

In-Depth Analysis of Structures, Materials, Models, Parameters, and Applications of Organic Light-Emitting Diodes

Organic electronics and specifically organic light-emitting diode (OLED) devices based on organic semiconductor materials enable economically viable large-area flexible applications. This review presents a comprehensive and detailed assessment of different aspects related to OLEDs, focusing on the impact of multilayered architectures on device performance, in particular the impact of different layers and architectures to enhance the output from such devices. Furthermore, characteristic parameters, materials, and fabrication methodologies are reviewed in depth to highlight the major advancements related to OLEDs over the years. Mathematical models are important for predicting the internal operation and characteristics of such devices, thus these are also discussed, focusing on methods to improve the performance parameters of OLEDs. Applications of OLEDs are also discussed, with a primary focus on research related to their improvement and enhancement for use in displays, sensors, and visual light communications. Although OLEDs show great promise for a bright future, several challenges such as the development of blue light-emitting materials, lifetime improvement, and application-specific architectures must be addressed to achieve more dynamic devices for emerging commercial applications.

AWARE-CNN: Automated Workflow for Application-Aware Real-Time Edge Acceleration of CNNs

This article presents the application-aware real-time edge acceleration of CNNs (AWARE-CNNs) accelerators, which is a novel architecture design methodology for real-time execution of deep learning algorithms on IoT devices. AWARE leverages the reconfigurability of field-programmable gate arrays (FPGAs) to create application-specific architectures customized to match the inherent dataflow of targeted deep neural networks and user-specified real-time requirements. The customized datapath is combined with a customized memory path to guarantee deterministic latency-aware execution over streaming data. For results and evaluation, we have developed a Chisel-based implementation of AWARE-CNN with a full integrative framework for application-specific architecture generation and synthesis (AWARE-CNN architecture compiler). Our results demonstrate the ability to execute Tiny DarkNet and shallow MobileNet inference at 120 frames/s (FPS) and 75 FPS, using only 2.8 and 3.4 W, respectively, on a Xilinx XCZU9EG FPGA. In addition, AWARE-CNN framework’s flexibility with respect to the targeted convolutional neural networks and user constraints is validated by targeting additional design points for AlexNet (as a baseline network) and Tiny YOLOv2.

Architectural Implication of Graph Neural Networks

Graph neural networks (GNN) represent an emerging line of deep learning models that operate on graph structures. It is becoming more and more popular due to its high accuracy achieved in many graph-related tasks. However, GNN is not as well understood in the system and architecture community as its counterparts such as multi-layer perceptrons and convolutional neural networks. This work tries to introduce the GNN to our community. In contrast to prior work that only presents characterizations of GCNs, our work covers a large portion of the varieties for GNN workloads based on a general GNN description framework. By constructing the models on top of two widely-used libraries, we characterize the GNN computation at inference stage concerning general-purpose and application-specific architectures and hope our work can foster more system and architecture research for GNNs.

Fog Computing: A Comprehensive Architectural Survey

Fog computing is an emerging technology to address computing and networking bottlenecks in large scale deployment of IoT applications. It is a promising complementary computing paradigm to cloud computing where computational, networking, storage and acceleration elements are deployed at the edge and network layers in a multi-tier, distributed and possibly cooperative manner. These elements may be virtualized computing functions placed at edge devices or network elements on demand, realizing the “computing everywhere” concept. To put the current research in perspective, this paper provides an inclusive taxonomy for architectural, algorithmic and technologic aspects of fog computing. The computing paradigms and their architectural distinctions, including cloud, edge, mobile edge and fog computing are subsequently reviewed. Practical deployment of fog computing includes a number of different aspects such as system design, application design, software implementation, security, computing resource management and networking. A comprehensive survey of all these aspects from the architectural point of view is covered. Current reference architectures and major application-specific architectures describing their salient features and distinctions in the context of fog computing are explored. Base architectures for application, software, security, computing resource management and networking are presented and are evaluated using a proposed maturity model.

Advanced Coatings by Thermal Spray Processes

Coatings are pivotal in combating problems of premature component degradation in aggressive industrial environments and constitute a strategic area for continued development. Thermal spray (TS) coatings offer distinct advantages by combining versatility, cost-effectiveness, and the ability to coat complex geometries without constraints of other in-chamber processes. Consequently, TS techniques like high-velocity oxy-fuel (HVOF) and atmospheric plasma spray (APS) are industrially well-accepted. However, they have reached limits of their capabilities while expectations from coatings progressively increase in pursuit of enhanced efficiency and productivity. Two emerging TS variants, namely high-velocity air-fuel (HVAF) and liquid feedstock thermal spraying, offer attractive pathways to realize high-performance surfaces superior to those hitherto achievable. Supersonic HVAF spraying provides highly adherent coatings with negligible porosity and its low processing temperature also ensures insignificant thermal ‘damage’ (oxidation, decarburization, etc.) to the starting material. On the other hand, liquid feedstock derived TS coatings, deposited using suspensions of fine particles (100 nm–5 µm) or solution precursors, permits the production of coatings with novel microstructures and diverse application-specific architectures. The possibility of hybrid processing, combining liquid and powder feedstock, provides further opportunities to fine tune the properties of functional surfaces. These new approaches are discussed along with some illustrative examples.

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors

Approximate computing has been exploited for many years in application-specific architectures. Recently, it has also been proposed for low-power programmable processors. However, this poses some challenges as, in a microprocessor, the energy consumed by fetching and decoding an instruction may be significantly higher than that of the execution itself. Therefore, approximate computing would be advisable only for those instructions, in which the execution stage is significantly expensive in terms of energy consumption. In this paper, we present new architectures for truncated SIMD multipliers able to calculate signed and unsigned products from $8\times {}8$ to $64\times {}64$ bits. Next, we analyze the precision loss incurred by truncation for all product sizes. We implement accurate and truncated architectures for both scalar and SIMD products and find that truncation allows area savings of up to 27%. The proposed design is experimentally evaluated in different scenarios, showing potential energy savings ranging from 29% to 42%. Finally, this paper analyzes the overall convenience of introducing truncated SIMD architectures with respect to accurate SIMD and scalar architectures.

IStore: Towards the Optimization of Federation File Systems

With the growing volumes of data, many organizations are deploying geo-distributed edge servers and building federations atop of edge servers to improve data sharing, effective collaborations, and analytics. Multiple federation file systems are designed to satisfy such needs, but due to application-specific architectures, these federations neglect some important features that can improve the overall federation performance. In this paper, we address the important challenges of federated file systems, in particular, global namespace, optimal data placement and analysis, efficient data migration across edge servers, and metadata optimizations. To further investigate these challenges, we prototyped the federation file system iStore to emulate the federation and showed the significance of the afore-mentioned key challenges in the federation. The iStore provides unified global namespace atop of geo-distributed edge servers with a generic job and resource-aware data storage and placement algorithm (JRAP), which minimizes the job execution time by considering resources at each edge server. Furthermore, to enable effective data migration, we employed direct channel file layout-aware data transfer and designed a batch-based metadata scheme for federations to reduce the metadata contention with increasing clients. We evaluated the efficacy of various big data applications from data generation to storage and analysis using the iStore on real testbed and simulation.

Implementation of application specific soft-core architecture for switching converters

Application Specific Processors (ASPs) are used in many areas. In this paper, an application specific soft-core processor for control of switching power converters is designed and implemented. The proposed designed architecture is constructed based on fixed-point arithmetic with minimal functional units. The control algorithm, which is used in this architecture, is Finite-Set Model Predictive Control (FS-MPC). The proposed soft-core processor is coded in VHSIC Hardware Description Language (VHDL) and implemented on Field-Programmable Gate Array (FPGA) platform. This architecture consists of minimum functional unit with only two adders and two multipliers, a control unit and a selection unit. The designed architecture is general and low cost and can be used in any type of converters. In this paper the functionality of the processor is examined by three types of converters namely three-phase inverters, dual transistor forward converter and active front end rectifier. In comparison with other controllers, output results indicate the accuracy of proposed architecture.

Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands

Embedded multi-core processors improve performance significantly and are desirable in many application-fields. This development, in particular, includes safety-critical real-time systems, which typically require a deterministic temporal behavior. However, even tasks without dependencies running on different cores can interfere due to, sometimes hidden, shared hardware resources, such as memory or communication buses. Consequently, only a pessimistic assumption of the worst-case execution time (WCET) that incorporates interference can be given. The desired performance gain therefore evaporates in the poor temporal analyzability. Safety-critical real-time systems are typically composed of multiple tasks with varying criticality levels and requirements on predictability and performance, respectively. In this paper, we present an approach that generates an application-specific, deterministic multi-core architecture for such mix-critical systems, thus eliminating the aforementioned hardware-induced interferences in the first place. Safety-critical tasks with stringent temporal requirements are mapped to dedicated Deterministic Execution Units (DEUs) while the remaining soft real-time tasks co-reside on a general purpose multi-core processor that offers performance over determinism. Just as well, predictable interconnections between DEUs are generated to satisfy dependencies and precedence constraints. Consequently, timing analysis for hard real-time tasks is significantly simplified, since interferences caused by shared resources and scheduling are finally eliminated. To show the benefits of our approach, an application-specific architecture for a flight controller was generated and compared to an ARM Cortex-A9 dual-core as a reference. Overall, we were able to significantly improve temporal properties of safety-critical tasks while preserving the overall performance for soft real-time tasks.

Referenceable mobile crowdsensing architecture: A healthcare use case

Smartphones have become an integral part in life of users, mainly because over the course of recent years, they have become extremely mainstream, cheap, flexible, and they pack high-end hardware that offers high computational capabilities. Many, if not all of today’s smartphones are equipped with sophisticated sensors which enable smart mobile sensing. The programmable nature of these sensors in the smartphones enable a wide array of possibilities to achieve user-centric or environmental sensing. Even though there have been different approaches proposed to develop a smartphone app, platform, design frameworks, APIs, and even application-specific architectures, there is a lack of generalised referenceable architecture in the literature. In this paper, we propose a generic reference architecture, which can be derived to create more concrete mobile sensing or mobile app architectures. Furthermore, we realise the proposed reference architecture in a healthcare use case, specifically in the context of applying smart mobile sensing to support tinnitus research.

Design of Application-Specific Architectures for Networked Labs-on-Chips

Labs-on-Chips (LoCs) implement laboratory procedures on a single chip and are successfully used for chemical and biomedical applications. A promising and emerging realization of such chips are Networked LoCs (NLoCs) in which small volumes of fluids, so-called droplets, flow in closed channels of submillimeter diameters. NLoCs allow for an incubation and storage of assays over a long period of time and, hence, avoid evaporation and unwanted reactions. To increase the flexibility, effectiveness, and reusability, network functionalities allow to passively route droplets in channels and, hence, to dynamically select operations depending on the executed experiment. However, only manually designed architectures are considered for NLoCs thus far. They frequently suffer from large execution times and/or a high contamination of channels. To overcome these drawbacks, we propose the consideration of application-specific architectures for NLoCs. To this end, an automatic design method is proposed which, for a given set of experiments as well as constraints and objectives from the designer, is able to generate an optimized NLoC architecture realizing these experiments. Evaluations and case studies demonstrate the potential of the proposed solution for design exploration. Moreover, we are able to show that application-specific architectures are capable of realizing experiments in just a fraction of the time needed by architectures used thus far as well as with a substantially reduced contamination.

Application-specific architectures for energy-efficient database query processing and optimization

Data processing on a continuously growing volume of data and the increasing power restrictions have become an ubiquitous challenge in our world today. Besides parallel computing, a promising approach to improve the energy efficiency of current systems is to integrate specialized hardware. This paper presents two application-specific architectures to accelerate basic database operators frequently used in modern database systems: an extended instruction set based on a given Cadence Tensilica processor (ASIP) and a comparable application-specific integrated circuit (ASIC). The ASIP is implemented in a system-on-chip and manufactured in a 28 nm CMOS technology to realize measurements of performance and power consumption. Furthermore, the comparison with the ASIC blocks allows to quantify the results with the ASIP approach in terms of throughput, area, and energy efficiency as well as to discuss the capabilities and limitations when accelerating selected database operators.

The cognitive systems toolkit and the CST reference cognitive architecture

Abstract In this paper, we introduce the Cognitive Systems Toolkit (CST) and its underlying CST Reference Cognitive Architecture. CST is a general toolkit for the construction of cognitive architectures, which relies on a set of concepts which are familiar to many other cognitive architecture and constitute CST’s core. This core is general enough such that problem-specific cognitive architectures might be generated by using CST. At the same time, CST specify a more general Reference Cognitive Architecture, which is a reference model for the construction of application specific cognitive architectures. Differently from other Cognitive Architectures available in the literature, which are computational frameworks, CST is a toolkit, which means more flexibility in choosing specific techniques and algorithms for setting up the application architecture. After presenting the architecture core, we develop an illustrative example showing how CST can be used to implement a simple subsumption architecture in a robotic application.

Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures

Digital microfluidic biochips (DMBs) are microfluidic devices that manipulate droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, and split, are performed on the electrode array to perform a biochemical application. All previous work assumes that the DMB architecture is given and most approaches consider a rectangular shape for the electrode array. However, nonrectangular application-specific architectures are common in practice. Hence, in this paper, we propose an approach to the synthesis of application-specific architectures, such that the cost of the architecture is minimized and the timing constraints of the biochemical application are satisfied. DMBs can be affected by permanent faults, which may lead to the failure of the biochemical application. Our approach introduces redundant electrodes to synthesize fault-tolerant architectures aiming at increasing the yield of DMBs. We have used a tabu search metaheuristic for this architecture synthesis problem. We have proposed a technique to evaluate the architecture alternatives visited during the search, in terms of their impact on the timing constraints of the application. The proposed architecture synthesis approach has been evaluated using several benchmarks.