Application-level Testing Research Articles

FPGA Qualification and Failure Rate Estimation Methodology for LHC Environments Using Benchmarks Test Circuits

When studying the behavior of a field programmable gate array (FPGA) under radiation, the most commonly used methodology consists in evaluating the single-event effect (SEE) cross section of its elements individually. However, this method does not allow the estimation of the device failure rate when using a custom design. An alternative approach based on benchmark circuits is presented in this article. It allows standardized application-level testing, which makes the comparison between different FPGAs easier. Moreover, it allows the evaluation of the FPGA failure rate independent of the application that will be implemented. The employed benchmark circuit belongs to the ITC’99 benchmark suite developed at Politecnico di Torino. Using the proposed methodology, the response of four FPGAs—the NG-Medium, the ProASIC3, the SmartFusion2, and the PolarFire—was evaluated under high-energy protons. Radiation tests with thermal neutrons were also conducted on the PolarFire to assess its potential sensitivity to them. Moreover, its performances in terms of total ionizing dose (TID) effects have been evaluated by measuring the degradation of the propagation delay during irradiation.

Acoustic response of high-speed deep groove ball bearing by modifying the internal geometry

In this paper, a mathematical model to predict acoustic responses of high-speed bearing has been developed and demonstrated in an application of Induction motors. Effect on the acoustic behaviour of bearing has studied by modifying the internal geometry, such as the number of rotating elements, curvature ratio, rotating speed with the oval shape of the track raceway due to pre-operational damage. The mathematical model predicts the contact stress, elliptical contact area, noise level dB and Frequencies of waviness pattern. High-speed bearing is tested at four different speeds to monitor acoustic behaviour. This drive end bearing undergoes different rotational speeds; however, the author has simulated the results at a majorly driven constant speed. The author has incorporated application-level testing at the customized test rig. The mathematical model has simulated using coupled governing equations with the help of the Ranga-Kutta method. The simulation and experimental results presented in this paper in the form of a waterfall diagram, FFT spectrum and colour pressure plots. Acoustic characteristics during measurements of the rolling bearing have shown systematically to correlate the mathematical model with an experimental result. Results indicate the remarkable influence of raceway nonconformities of bearing on the noise level. The novelty of research study is to estimate the amplitude of noise level due to waviness generated on rings of bearing after pre-operation damage which is the realistic scenario that occurred after a complaint recorded by the motor manufacturer. The authors believe that this technique enables the bearing designer to choose the appropriate diametric ratio of the ball and track curvature for elliptical contact stress as well as acoustic level. This method is developed specifically for an application of drive-end position ball bearing. Practical use of this method is to determine the Noise level of an electric motor (up to 60 kW capacities) due to improper handling and inappropriate installation of bearing which cause inherent waviness on components.

FPGA Auto Configuration Based on ATE

FPGAs (Field Programmable Gate Arrays) are highly integrated devices which can be programmed as variable functions. The application-level testing of FPGAs usually include multiple reconfigurations and relevant functional tests respectively through ATEs (Automated Test Equipments). However, test engineers are facing a tough problem to reconfigure FPGAs automatically through an ATE instead of using specific tools and download cables provided by FPGAs manufacturers. This paper takes example for XILINX Virtex-E series, presents two different methods for FPGA auto configuration based on an ATE using JTAG configuration interface and boundary-scan protocol, and accomplishes the entire auto configuration-test procedure by a single ATE.