Application-level Analysis Research Articles

A scenario- and platform-aware design flow for image-based control systems

Image-based control (IBC) systems are increasingly being used in various domains including autonomous driving. The key challenge in IBC is to deal with high computation demand while guaranteeing performance and safety requirements such as stability. While modern industrial heterogeneous platforms, such as NVIDIA Drive, offer the necessary compute power, application development on these platforms with performance and safety guarantees is still challenging. Alternative time-predictable platforms are not yet in widespread use.A typical design flow for IBC systems consists of three distinct elements: (i) mapping tasks onto platform resources; (ii) timing analysis, consisting of task-level worst-case execution time (WCET) analysis and application-level analysis to obtain worst-case performance bounds on aspects such as latency and throughput; (iii) controller design using the obtained performance bounds, ensuring performance and safety. While such a three-step design process is modular in nature, it usually leads to over-dimensioned systems with sub-optimal performance, because task- and/or application-level timing bounds are pessimistic.We present a scenario- and platform-aware design flow for IBC systems that exploits frequently occurring workload scenarios to optimize performance. For industrial platforms, where tight task-level WCET bounds are difficult to obtain, we moreover propose to use frequently occurring task execution times instead of WCET estimates to obtain tight application-level temporal bounds. During controller design, we then optimize performance and guarantee stability by identifying appropriate system scenarios and by designing a switched controller that switches between those scenarios. We illustrate our method considering a predictable multiprocessor system-on-chip platform - CompSOC. We validate the proposed method using hardware-in-the-loop (HiL) experiments with an industrial heterogeneous multiprocessor platform - NVIDIA Drive PX2 - considering a lane keeping assist system (LKAS). We obtain an improved control performance compared to state-of-the-art IBC design.

Performance-Aware Scheduling of Parallel Applications on Non-Dedicated Clusters

This work presents a HPC framework that provides new strategies for resource management and job scheduling, based on executing different applications in shared compute nodes, maximizing platform utilization. The framework includes a scalable monitoring tool that is able to analyze the platform’s compute node utilization. We also introduce an extension of CLARISSE, a middleware for data-staging coordination and control on large-scale HPC platforms that uses the information provided by the monitor in combination with application-level analysis to detect performance degradation in the running applications. This degradation, caused by the fact that the applications share the compute nodes and may compete for their resources, is avoided by means of dynamic application migration. A description of the architecture, as well as a practical evaluation of the proposal, shows significant performance improvements up to 20% in the makespan and 10% in energy consumption compared to a non-optimized execution.

NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs

The tremendous impact of deep learning algorithms over a wide range of application domains has encouraged a surge of neural network (NN) accelerator research. An evolving benchmark suite and its associated benchmark method are needed to incorporate emerging NN models and characterize NN workloads. In this paper, we propose a novel approach to understand the performance characteristic of NN workloads for accelerator designs. Our approach takes as input an application candidate pool and conducts an operator-level analysis and application-level analysis to understand the performance characteristics of both basic tensor primitives and whole applications. We conduct a case study on the TensorFlow model zoo by using this proposed characterization method. We find that tensor operators with the same functionality can have very different performance characteristics under different input sizes, while operators with different functionality can have similar characteristics. Additionally, we observe that without operator-level analysis, the application bottleneck is mischaracterized for 15 out of 57 models from the TensorFlow model zoo. Overall, our characterization method helps users select representative applications out of the large pool of possible applications, while providing insightful guidelines for the design of NN accelerators.

Die crack failure mechanism investigations depending on the time of failure

The quality and reliability concern of the die crack failure mechanism needs to be addressed at each step of the supply chain, from the wafer supplier, semiconductor fabrication, package assembly, Tier1 manufacturer assembly, to the end customer application. Finding the critical factors of a die crack is crucial for the root cause investigation, allowing the implementation of accurate corrective actions. The various analytical methods that can be employed are numerous, from standard FA techniques (mainly SAM & fractography) to advanced techniques like TherMoiré Analysis or Finite Element Simulation. Application-level analysis, problem solving and continuous improvement methodologies are also key success factors for such problems: Fault Tree Analysis and Ishikawa diagram will enable complete process assessment, including package and die integrity, assembly process, Surface-mount technology (SMT) process, and stress condition at the end customer application. This paper first introduces the different and complementary FA techniques, then presents three case studies that illustrate the difficulty to identify the cause of such die cracks, as a function of the time of failure.

Motion Compensation of Tendon-Sheath Driven Continuum Manipulator for Endoscopic Surgery

Tendon-sheath actuation mechanism is widely used in surgical robot, especially in endoscopic surgery, due to its capable of providing remote force and action transmission through long and flexible channel. However, hysteresis, backlash, nonlinear friction are the drawbacks of this mechanism. Our surgical robot use continuum manipulator which is useful in endoscopic surgery, due to its flexible and simple structure. Unlike other literatures that focus on tendon-sheath compensation only, the continuum manipulator is also taken into application level analysis. A model based feedforward motion compensation for tendon-sheath driven continuum manipulator is presented. The model is validated by using optical tracking system to trace the distal end position. Experiment result shows that the proposed model reduces the position error less than 5%.

A Strict-Observational Interface Theory for Analysing Service Orchestrations

Service oriented computing is an accepted architectural style for developing large, distributed software systems. A particular promise of such architectures is service orchestration, i.e. the ability to combine existing services to create more complex functionality, thereby yielding new services. In this paper, we discuss application-level protocol compliance checking of service orchestrations and service protocols using the semantic domain of modal input/output automata (MIOs). Based on a practical example, we motivate and introduce new notions of refinement and compatibility, and prove that they constitute a valid interface theory. With this domain-specific interface theory, we provide a framework for application-level analysis of service orchestrations, thus complementing existing work on compatibility analysis. Our theory is tool-supported through the MIO Workbench, a verification tool for modal input/output automata.

The future of intrusion prevention

The future of intrusion prevention is likely to be marked by significant technical advances, but currently it is still strongly supported by its technological predecessor. Despite predictions by IT analyst Gartner – in 2003 – that Intrusion Detection Systems (IDS) would be history by now – replaced by Intrusion Protection Systems (IPS), the former is still going strong. Dr Gene Shultz says that security professionals are increasingly seeing IDS and IPS as two overlapping but different technologies and IDS sales have continued to grow. Nevertheless IPS continues to grow popular. This issue of Computer Fraud & Security looks at four predictions for the technology's future. Dr Gene Schultz believes the improvements of IDS, which provides the foundations for IPS, will buoy the latter along. He says zero day attacks that systems may have failed to detect seven years ago are now being found. Also, IPSs are set to play a larger role in forensics data preservation by providing data to a forensics server while preserving the integrity of the data. “More advanced response capabilities will allow users and organizations to choose from a wide range of response mechanisms as well as fine tune them to more closely meet their business and operational needs,” says Schultz. The big four predictions:Prediction 1: Better underlying intrusion detectionPrediction 2: Advancements in application-level analysisPrediction 3: More sophisticated response capabilitiesPrediction 4: Integration of intrusion prevention into other security devices The big four predictions: Prediction 1: Better underlying intrusion detection Prediction 2: Advancements in application-level analysis Prediction 3: More sophisticated response capabilities Prediction 4: Integration of intrusion prevention into other security devices Intrusion prevention has gained in popularity to the point where it is now widely considered a mainstream security technology. Intrusion prevention is similar to intrusion detection in that it is designed to identify potential and actual security breaches in near-real time, but intrusion prevention goes farther than intrusion detection in that it provides the ability to respond defensively to attacks, thereby preventing them from succeeding – at least in the ideal case. Because so many attacks occur so swiftly, automated mechanisms designed to thwart them may not be able to stop them from initially succeeding, however. In such cases, intrusion prevention mechanisms often attempt to prevent the attack from spreading any farther.

Measuring adversaries

Many concepts and techniques developed for general Internet measurement have counterparts in the domain of detecting and analyzing network attacks. The task is greatly complicated, however, by the fact that the object of study is adversarial : attackers do not wish to be "measured" and will take steps to thwart observation. We look at the far-ranging consequences of this different measurement environment: the analysis difficulties-some fundamental-that arise due to subtle ambiguities in the true semantics of observed traffic; new notions of "active measurement"; the highly challenging task of rapidly characterizing Internet-scale pheonmena such as global worm pandemics; the need for detailed application-level analysis and related policy and legal difficulties; attacks that target passive analysis tools; and the inherent "arms race" nature of the undertaking.

Asynchronous parallel simulation of parallel programs

Parallel simulation of parallel programs for large datasets has been shown to offer significant reduction in the execution time of many discrete event models. The paper describes the design and implementation of MPI-SIM, a library for the execution driven parallel simulation of task and data parallel programs. MPI-SIM can be used to predict the performance of existing programs written using MPI for message passing, or written in UC, a data parallel language, compiled to use message passing. The simulation models can be executed sequentially or in parallel. Parallel execution of the models are synchronized using a set of asynchronous conservative protocols. The paper demonstrates how protocol performance is improved by the use of application-level, runtime analysis. The analysis targets the communication patterns of the application. We show the application-level analysis for message passing and data parallel languages. We present the validation and performance results for the simulator for a set of applications that include the NAS Parallel Benchmark suite. The application-level optimization described in the paper yielded significant performance improvements in the simulation of parallel programs, and in some cases completely eliminated the synchronizations in the parallel execution of the simulation model.