Anisotropic Etching Step Research Articles

Trimming method for a high-yield manufacturing of high-efficiency diffraction gratings.

The tolerances in manufacturing of fully dielectric diffraction gratings based on the leaky-mode resonance in the -1st diffraction order can be challenging, especially if the grating design exhibits high diffraction efficiency (DE) only within a comparatively narrow spectral bandwidth. To gain improved control on the spectral bandwidth exhibiting high DE, we implemented a two-step etching approach within the fabrication process of the grating. First, a dry and anisotropic etching step was used for pre-shaping the grating, followed by iterative isotropic wet-etching steps using an alkaline solution (KOH) at a temperature of 90°C to adjust the maximum efficiency around the desired wavelength with high precision. This straightforward method gave us very good control on tailoring the DE as a function of the wavelength and led to the demonstration of DEs as high as 99.7±0.2% in the -1st diffraction order at a wavelength of 1030nm and of >99% in the wavelength range between 1020 and 1070nm. The gratings were used as cavity end mirrors of an Yb:YAG thin-disk laser, generating an output power of 145W in fundamental mode operation (M2<1.1).

Optimization of hybrid organic/inorganic poly(3-hexylthiophene-2,5-diyl)/silicon solar cells

In the last years, hybrid organic/silicon solar cells have attracted great interest in photovoltaic research due to their potential to become a low-cost alternative for the conventionally used silicon pn-junction solar cells. This work is focused on hybrid solar cells based on the polymer poly(3-hexylthiophene-2,5-diyl), which was deposited on n-doped crystalline silicon via spin-coating under ambient conditions. By employing an anisotropic etching step with potassium hydroxide (KOH), the reflection losses at the silicon surface were reduced. Hereby, the short-circuit current density of the hybrid devices was increased by 31%, leading to a maximum power conversion efficiency (PCE) of 13.1% compared to a PCE of 10.7% for the devices without KOH etching. In addition, the contacts were improved by replacing gold with the more conductive silver as top grid material to reduce the contact resistance and by introducing a thin (∼0.5 nm) lithium fluoride layer between the silicon and the aluminum backside contact to improve electron collection and hole blocking. Hereby, the open-circuit voltage and the fill factor of the hybrid solar cells were further improved and devices with very high PCE up to 14.2% have been realized.

Improved thermal isolation of silicon suspended platforms for an all-silicon thermoelectric microgenerator based on large scale integration of Si nanowires as thermoelectric material

Special suspended micro-platforms have been designed as a part of silicon compatible planar thermoelectric microgenerators. Bottom-up grown silicon nanowires are going to bridge in the future such platforms to the surrounding silicon bulk rim. They will act as thermoelectric material thus configuring an all-silicon thermoelectric device. In the new platform design other additional bridging elements (usually auxiliary support silicon beams) are substituted by low conductance thin film dielectric membranes in order to maximize the temperature difference developed between both areas. These membranes follow a sieve-like design that allows fabricating them with a short additional wet anisotropic etch step.

Smooth silicon sidewall etching for waveguide structures using a modified Bosch process

We present a method to etch vertical and smooth silicon sidewalls. The so-called modified Bosch process combines a passivation step, a breakthrough step, and an anisotropic etch step within one repeatable loop. Thanks to the sidewall protection from the passivation step and the anisotropic nature of the etch step, this method can etch smoother silicon sidewalls than either a typical Bosch process or a continuous anisotropic etch process. The silicon sidewall of a 4-μm-deep waveguide structure etched by this method has a root mean square roughness below 10 nm and a peak-to-valley (P-V) roughness below 60 nm. Comparisons between silicon waveguides etched by this process and by another deep reactive-ion etching process showed remarkable improvement in propagation loss at the wavelength of 1550 nm.

Fabrication of inverse micro/nano pyramid structures using soft UV-NIL and wet chemical methods for residual layer removal and Si-etching

In this study we present a novel and simple fabrication method for micro- and nano-scale inverse pyramidal structures by a combination of soft UV-NIL and wet chemical etchings. The unique feature of our method is the absence of a RIE process, which is usually applied for removal of residual layer. This is achieved by modifying the imprint resist with an O2-plasma in asher and subsequent wet etching of residual layer by diluted HF. Combined with conventional anisotropic wet etching step with KOH/IPA, our method allows cost effective fabrication of inverse pyramidal structures on Si-substrate in batch process. Such structures in nano- and micro scale are particularly suitable for light management in photovoltaic, solid state lighting and silicon based photonic.

Polymer as the protecting passivaton layer in fabricating suspended SCS structures in both anisotropic and isotropic etching

This paper presents a rapid bulk micromachining process named polymer passivation layer for suspended structures etching by using a polymer as a protecting passivation layer at both anisotropic and isotropic etching steps. Without using silicon-dioxide (SiO2) deposition or boron doping as a protection layer at the releasing step, the proposed method can fabricate suspended single-crystal silicon structures in an inductively coupled plasma reactive ion etching chamber directly, which would simplify the fabrication process and save fabrication time. The current study systematically investigates critical fabrication parameters to verify the feasibility of the proposed method, and discusses the polymer passivation time and removal time of a polymer at the base of a substrate at four different opening gaps of 5, 10, 30 and 50 µm with the 30 µm deep trench to establish suitable recipes for fabricating suspended microstructures. It is also shown that the proposed method can fabricate not only the suspended microstructures with the same thickness, but also suspended microstructures with different thicknesses, as well as in sub-micro scale.

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via’s with a good control over the walls angles for two etching windows sizes (100 and 20 μm respectively) on 300 μm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3° and 21.8°. Barrier and seed layers were deposited in via’s performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.

Implant Defined Anti-Guided Vertical-Cavity Surface-Emitting Laser Arrays

Anti-guided vertical-cavity surface-emitting laser (VCSEL) arrays can be designed to consistently operate in-phase, i.e., with a narrow, on-axis peak in the far field. However, the fabrication of such arrays typically requires anisotropic etching and epitaxial regrowth steps. We have found that anti-guiding behavior can be realized in implant-defined VCSEL arrays. The primary advantage is that the laser arrays can be designed to operate in-phase without requiring any fabrication steps more complicated than those used for conventional implant VCSELs. We present our array structure, a theoretical treatment of the anti-guiding confinement, and experimental results showing the behavior characteristic of anti-guided arrays.

“Mesh-assisted” colloidal lithography and plasma etching: A route to large-area, uniform, ordered nano-pillar and nanopost fabrication on versatile substrates

We propose a variation of colloidal (microparticle) lithography, which we term “mesh-assisted” colloidal lithography, to improve uniformity and quality of monolayer microparticle assembly over large areas: a square mesh with 200–1000μm open squares (total open-area larger than 75%) and of appropriate height is created/placed on a substrate surface, and acts as template facilitating uniform, monolayer assembly of polystyrene (PS) microparticles with spin-coating. We also study the pattern transfer, the pillar/post formation and their dimensional control on several substrates, namely polymers, silicon and silicon dioxide. Highly ordered nanopillar or nanopost arrays are produced on: (a) PMMA plates by one anisotropic etching step, (b) silicon, and (c) silicon dioxide. The silicon nanopillars and silicon dioxide nanoposts are fabricated by a two step plasma etching: an isotropic oxygen plasma step which shrinks the PS microspheres followed by an anisotropic step to transfer the pattern. The obtained pillars have nanotexture on top of the PS sphere due to plasma roughening, and thus present dual-scale topography, useful for applications such as superhydrophobic surfaces. Our method is thus a combination of photolithography, colloidal lithography, and plasma etching for low-cost, large area nanopost formation.

Micromachining of Multilayer Thin Films for High-Speed Humidity Sensor Fabrication

This paper reports the microfabrication and characteristics of a novel high-speed polyimide-based humidity sensor using an etch process based on a combination of isotropic and anisotropic etching steps with inductively coupled plasma (ICP) and a localized curing of polyimide films on microhotplate. The polyimide capacitive humidity sensors showed a sensitivity of 0.77 pF/percent relative humidity (%RH), a linearity of 0.9995, and a hysteresis of 0.62%RH, a response time of 3 s. In comparison, the sensors with a conventional structure exhibited a time response of 7 s. High speed is achieved because a device has many holes and moisture is thus absorbed into the top and side surfaces of polyimide.

Advanced Wet Etch Bulk Micromachining in {100} Silicon Wafers

AbstractIn this work we have developed novel microfabrication processes using wet anisotropic etchants to perform advanced bulk micromachining in {100}Si wafers for the realization of microelectromechanical systems (MEMS) structures with new shapes. The etching is performed in two steps in pure and Triton-X-100 [C14H22O(C2H4O)n, n = 9-10] added 25 wt% tetramethyl ammonium hydroxide (TMAH) solutions. The local oxidation of silicon (LOCOS) is attempted after the first anisotropic etching step in order to protect the exposed silicon. Two types of structures (fixed and freestanding) are fabricated. The fixed structures contain perfectly sharp corners and edges. Thermally grown silicon dioxide (SiO2) is used for the fabrication of freestanding structures. Present research is an approach to fabricate advanced MEMS structures, extending the range of 3D structures fabricated by silicon wet anisotropic etching.

Fabrication and Characterization of Silicon Micro-Funnels and Tapered Micro-Channels for Stochastic Sensing Applications.

We present a simplified, highly reproducible process to fabricate arrays of tapered silicon micro-funnels and micro-channels using a single lithographic step with a silicon oxide (SiO2) hard mask on at a wafer scale. Two approaches were used for the fabrication. The first one involves a single wet anisotropic etch step in concentrated potassium hydroxide (KOH) and the second one is a combined approach comprising Deep Reactive Ion Etch (DRIE) followed by wet anisotropic etching. The etching is performed through a 500 μm thick silicon wafer, and the resulting structures are characterized by sharp tapered ends with a sub-micron cross-sectional area at the tip. We discuss the influence of various parameters involved in the fabrication such as the size and thickness variability of the substrate, dry and wet anisotropic etching conditions, the etchant composition, temperature, diffusion and micro-masking effects, the quality of the hard mask in the uniformity and reproducibility of the structures, and the importance of a complete removal of debris and precipitates. The presence of apertures at the tip of the structures is corroborated through current voltage measurements and by the translocation of DNA through the apertures. The relevance of the results obtained in this report is discussed in terms of the potential use of these structures for stochastic sensing.

Fabrication and fluidic characterization of silicon micropillar array electrospray ionization chip

A silicon electrospray ionization (ESI) chip for the mass spectrometric analysis is designed, fabricated, and characterized. The chip has three parts: a liquid sample introduction spot, a flow channel, and a sharp electrospray ionization tip. A regular micropillar array is micromachined inside the whole channel. The chip has no lid, which makes the sample application and chip fabrication easier. A two photomask level fabrication process utilizes nested masks of silicon dioxide and aluminum oxide. A combination of anisotropic and isotropic plasma etching steps allows formation of a truly three-dimensional electrospray ionization tip without double-sided lithography. The filling properties of the lidless micropillar channel are studied. Because of the capillary forces facilitated by the micropillar array, the sample applied onto the sample introduction spot spontaneously fills the whole flow channel including the electrospray ionization tip, without external pumping. Besides reliable self-filling, the chip offers stable electrospraying and high sensitivity chemical analysis when coupled to a mass spectrometer (MS).

A-Si:H based two-dimensional photonic crystals

We describe the fabrication processes of silicon-based two-dimensional photonic crystals (2D-PCs) with a photonic band gap in the near-IR range. The procedures involve electron beam lithography followed by an anisotropic etching step of hydrogenated amorphous silicon thin films deposited by plasma enhanced chemical vapor deposition. Micrometric and submicrometric arrays of cylindrical holes are transferred using a poly-methylmethacrylate resist layer as a mask. A careful comparison between standard parallel plate reactive ion etching and inductively coupled plasma etching techniques is performed, aimed at obtaining periodic structures with high aspect ratio and good profile sharpness.

Fabrication of microsuspensions on silicon substrate

A new technique to remove the silicon from beneath a large structure, by micromachining for making a suspended microstructure both for thermal, as well as electromagnetic, isolations on a complementary metal-oxide-semiconductor (CMOS) chip is reported. Conventional methods require two step front-side etching, an isotropic step, followed by an anisotropic etching step. An alternative technique is based on the backside etching process, which requires extra masks, and processing steps. In order to keep the postprocessing steps to a minimum, a simple technique has been developed that exploits the front-side anisotropic etching to create both undercuttings as well as deep etching in one single step. This method uses the gate oxide and polysilicon layer in CMOS technology as the sacrificial layer for initiating the undercutting needed to make a freestanding microstructure. The microsuspension thickness, width and length of 2 μm, 150 μm×150 μm, respectively, are made out of low-pressure chemical vapor deposition oxide and have been fabricated.

Dry etching with gas chopping without rippled sidewalls

In the last years, silicon micromachining techniques based on high aspect ratio reactive ion etching with gas chopping have been developed. There the gas flow of etching and deposition gas precursors is chopped which results in controllable sidewall passivation and high anisotropy. However, the rippled sidewalls are a serious limit for various applications. We report on the development of a novel gas chopping etching technique (GCET) process in order to achieve a smooth (rippled free) sidewall surface. As the direct etch mask, we used a 1 or 2-μm-thick resist layer, which was lithographically patterned. The novelty of the process consists in the replacing of the isotropic etching step by an anisotropic etching step. In this way we omit the main source for sidewall ripples. GCET combined with inductively coupled plasmas and fluorine chemistry provide very high etch rates and good control of the sidewall slope. These techniques also can be applied to conventional reactive ion etching equipment with Cl or F based plasma chemistry. However, the techniques used in this study have lower selectivity (in range of 30) than the conventional GCET. A SiON/Si selectivity as high as 50 has been achieved.

The correlation between surface morphology and spectral lineshape: a re-examination of the H–Si(111) stretch vibration

The effects of atomic-scale etch pits, anisotropic etching, and surface steps on the lineshape of the Si–H stretch vibration are studied using realistic kinetic Monte Carlo simulations of etched Si(111) surfaces. All three morphological features lead to a red shift in the in-phase vibrational mode, which is due to decreased dynamic dipole coupling. Pitted surfaces have an asymmetrically broadened vibrational lineshape because the decreased symmetry lends oscillator strength to higher-order vibrational modes. A much smaller asymmetry is seen in spectra of anisotropically etched surfaces. Previous estimates of the perfection of NH 4F-etched Si(111) surfaces, which were based on infra-red lineshape measurements, are shown to overestimate the quality of the etched surfaces.

Design and processing experiments of a new miniaturized capacitive triaxial accelerometer

A new accelerometer design is presented, which enables accelerations to be measured along three axes by using only one seismic mass. Two versions have been designed. The larger version has an input range of ± 8 g and a relative capacitance change of about 200% (full scale). The smaller version has an input range of ±10 g and a relative capacitance change of about 100% (full scale). The dimensions are 5 mm × 4.8 mm × 1.4 mm and 2.2 mm × 2.0 mm × 1.3 mm, respectively. The chosen technology is bulk micromachining, so the seismic mass is fabricated in an anisotropic wet etch step. The etchant is aqueous KOH, saturated with isopropyl alcohol. A 〈110〉 strip corner undercutting compensation technique has been adapted. It is shown that a full three-axis accelerometer can be fabricated in silicon by adapting the state-of-the-art micromachining tools.

Hybrid postprocessing etching for CMOS-compatible MEMS

A major limitation in the fabrication of microstructures as a postCMOS (complimentary metal oxide semiconductor) process has been overcome by the development of a hybrid processing technique, which combines both an isotropic and anisotropic etch step. Using this hybrid technique, microelectromechanical structures with sizes ranging from 0.05 to /spl sim/1 mm in width and up to 6 mm in length were fabricated in CMOS technology. The mechanical robustness of the microstructures determines the limit on their dimensions. Examples of an application of this hybrid technique to produce microwave coplanar transmission lines are presented. The performance of the micromachined microwave coplanar waveguides meets the design specifications of low loss, high phase velocity, and 50 /spl Omega/ characteristic impedance. Various commonly used etchants were investigated for topside maskless postmicromachining of <100> silicon wafers to obtain the microstructures. The isotropic etchant used is gas-phase xenon difluoride (XeF/sub 2/), while the wet anisotropic etchants are either ethylenediamine-pyrocatechol (EDP) or tetramethylammonium hydroxide (TMAH). The advantages and disadvantages of these etchants with respect to selectivity, reproducibility, handling, and process compatibility are also described.

Fabrication of Si Nanostructures for Single Electron Device Applications by Anisotropic Etching

Si nanostructures for single electron device applications are successfully fabricated using a newly developed anisotropic etching technique . The minimum size of the Si nanostructures is about 10 nm, which is much smaller than the lithography limit. The novel process involves two anisotropic etching steps and one selective oxidation step, and is fully compatible with very large scale integration (VLSI) processes. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) observations indicate that the fabricated nanostructures are very uniform and atomically controlled. This process is promising for the future integration of single electron devices into VLSI chips.