And-or-inverter Research Articles

An Efficient Module for Full Adders in Quantum-dot Cellular Automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work.

Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder

The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter (BEC) and a Parallel Prefix Adder. The delay of the Modified Linear Carry Select Adder of Brent Kung Adder is less when compared with the Regular Carry Select Adder architecture. The delay and area further can be improved by using a Square root Carry Select adder. This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder. Keywords: And-Or-Inverter (AOI) Logic, Binary-to-Excess-1 Converter (BEC), Brent-Kung (BK) Adders, Carry Select Adder (CSLA), Parallel Prefix Adder

Design and Simulation of Low Power and Area Efficient SQRT Carry Select Adder with Modified Binary to Excess-1 Converter

In the design of Integrated circuits, area occupancy and power consumption plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor level modification of EX-OR gate used in BEC-1 converter to significantly reduce the area and power of the CSLA. Based on this modification 4, 8, 16-bit SQRT CSLA architecture have been developed and compared with the SQRT CSLA architecture using AND, OR, INVERTER (AOI) implementation of EX- OR gate used in BEC-1 converter. The proposed SQRT CSLA is designed in 130 nm technology. The proposed design has reduced area and power as compared with the SQRT CSLA using ordinary BEC-1 converter. This work evaluates the performance of the proposed designs in terms of area and power. The results analysis shows that the proposed SQRT CSLA structure is better than the regular SQRT CSLA.

Design of logical structures and characteristics analysis of AOI for quantum dot cellular automata

Quantum dot Cellular Automata (QCA) offers a new transistorless computing paradigm in nanotechnology. It has the potential for attractive features such as faster speed, smaller size and low power consumption than transistor based technology. By taking the advantages of QCA we are able to design interesting computational architecture. The basic logic elements used in this technology are the inverter and the majority gate (MG). The majority gate is not a universal gate. Hence another important logic gate introduced in this technology is And-Or-Inverter (AOI). In this paper, we propose design of different logical structures using AOI. The rules are introduced in this paper for easy implementation of AOI circuits for different functions and characteristics of AOI is also defined and analyzed. Design implementations using the AOI gate are compared with the conventional CMOS and majority gate based QCA methodology.

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

Quantum-dot cellular automata (QCA) offers a new computing paradigm for nanotechnology. The basic logic elements of this technology are the majority voter (MV) and the inverter (INV). However, an experimental evaluation has shown that MV is not efficiently used during technology mapping by existing logic-synthesis tools. In this paper, we propose the design and characterization of a novel complex, yet very small, QCA logic gate: the and-or-inverter (AOI) gate. The paper presents a detailed simulation-based analysis of the AOI gate, as well as the study of QCA defects and their effects at the logic level. The AOI implements a universal logic gate; all elementary gates can be implemented by the AOI gate. Moreover, many two-level logic functions can be directly implemented by a single AOI gate. The AOI gate performs quite favorably, in terms of digital logic synthesis. Unlike MV, this gate is efficiently used by existing logic-synthesis tools. Our experimental data on synthesis of complex designs show that using the AOI gate instead of MV, results in up to 23.9% logic area savings, while improving the overall delay.

Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications

Efficient physical timing models for complex CMOS AND-OR-inverter (AOI) and OR-AND-inverter (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS AOI/OAI gates with wide ranges of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% with the commonly used device dimensions. The developed timing models are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a good accuracy and a reasonable CPU time consumption. >