Ancient Indian Vedic Mathematics Research Articles

Comparative Analysis of Vedic Multiplier using Various Adder Architectures

The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

A Multiplier Design based on Ancient Indian Vedic Mathematics Using Reversible Logic: A Review

A Multiplier Design based on Ancient Indian Vedic Mathematics Using Reversible Logic: A Review

Some Techniques of Ancient Indian Vedic Mathematics for Elliptic Curve Cryptography over the Ring A4

International Journal of Computer Sciences and Engineering (A UGC Approved and indexed with DOI, ICI and Approved, DPI Digital Library) is one of the leading and growing open access, peer-reviewed, monthly, and scientific research journal for scientists, engineers, research scholars, and academicians, which gains a foothold in Asia and opens to the world, aims to publish original, theoretical and practical advances in Computer Science,Information Technology, Engineering (Software, Mechanical, Civil, Electronics & Electrical), and all interdisciplinary streams of Computing Sciences. It intends to disseminate original, scientific, theoretical or applied research in the field of Computer Sciences and allied fields. It provides a platform for publishing results and research with a strong empirical component. It aims to bridge the significant gap between research and practice by promoting the publication of original, novel, industry-relevant research.

Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.

Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics

Multiplication is the most time consuming process in various signal processing operations like Convolution, Circular Convolution, auto-correlation, and Cross Correlation, Image processing applications such as edge detection, microprocessors arithmetic and logical units etc. The multiplier circuit uses adder logic which reduces speed of operation due to its path propagation delay. The designs used offer tradeoffs between Computational time area, latency and throughput for performing multiplication. In this paper an ancient Indian Vedic mathematics sutras base multiplier have been proposed with Urdhva Tiryakbhyam sutra. In this methodology the length of input sequence used for multiplication varies from two to eight.

A Review on Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

RSA is one of the most safest standard algorithm based on public key, for providing security in network. The hierarchical overlay multiplier is used in RSA circuitry for multiplication operation. The most significant aspect is the development of division architecture based on Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. Typically, modularmultiplication algorithm is used since no trial division is necessary, and the carry-save addition (CSA) is employed to reduce the critical path. The implementation of RSA encryption/decryption algorithm using the algorithm of Ancient Indian Vedic Mathematics that have been modified to improve performance. RSA circuitry implemented using vedic multiplication is efficient in terms of area, speed compared to its implementation using conventional multiplication. Keywords— RSA Cryptosystem, Modular Multiplication,, Modular exponentiation, Vedic Mathematics, FPGA, VHDL. __________________________________________________*****_________________________________________________

High Performance Novel Square Root Architecture Using Ancient Indian Mathematics for High Speed Signal Processing

Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson’s (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.

Ancient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors

The use of Vedic mathematics lies in the fact that it reduces the typical calculation in the conventional mathematics to very simple once. This is so because the Vedic formulae have claimed to be building on the natural principles on which the human mind works. Vedic mathematics is a several effective algorithms, which has spread over to various branches of engineering such as computing. In computers, typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operation. In this work, I have studied different multipliers, which give low power requirement and high speed, also give information of “urdhva-Tiryabhyam” algorithm of ancient Indian Vedic mathematics, which has utilized for multiplication to improve speed of multipliers. The proposed algorithm has modeled using VHDL, a hardware descriptive language. In a work I have simulated and synthesized 32-bit multiplier, the result shows that multiplier implemented using Vedic multiplication is efficient in terms of speed.

Vedivision – A Fast Bcd Division Algorithm Facilitated by Vedic Mathematics

Of the four elementary operations, division is the most time consuming and expensive operation in modern day processors. This paper uses the tricks based on Ancient Indian Vedic Mathematics System to achieve a generalized algorithm for BCD division in a much time efficient and optimised manner than the conventional algorithms in literature. It has also been observed that the algorithm in concern exhibits remarkable results when executed on traditional mid range processors with numbers having size up to 15 digits (50 bits). The present form of the algorithm can divide numbers having 38 digits (127 bits) which can be further enhanced by simple modifications.

Implementation of an Efficient Multiplier Architecture over a Conventional Methods using Ancient Indian Vedic Sutra

Fast multiplication is very important in processing of digital signals like DSP for convolution, Fourier Transform, etc. Many conventional methods are used for designing a multiplier for processing a digital signal. In this paper, A fast method for multiplication based on Ancient Indian Vedic mathematics is proposed. The whole of Vedic mathematics is based on 16 sutras (formulae). Among the various methods of multiplication in Vedicmathematics, Urdhava Tiryakbhyam (Vertically and Crosswise) is discussed in detail. This is the general multiplication formula applicable to all cases of multiplication. For implimentation of a efficient Architecture simple Boolean logic is combined with Vedic formulas, which reduces the partial products and sums generated in one step. The coding is done in VHDL and synthesis is done using Xilinx ISE 9. 1i simulator. Results are compaired with several conventional techniques.

An Efficient Design of Vedic Multiplier using new Encoding Scheme

This paper presents a design of efficient Digital Vedic Multiplier using the Vedic sutras from ancient Indian Vedic mathematics. If we are looking towards the signal processing, we will find multipliers and adders plays a very important roll. In fact if we make our focus we can see speed of the Digital signal processing systems is mainly dependent on multipliers and adders. A processor requires more hardware and processing time during multiplication rather than addition and subtraction. In this paper we proposed a new digital Vedic multiplier structure based on a new encoding algorithm. We found that this algorithm reduces the number of partial products so reduces the adders. Thus multiplier is going to faster. In this paper we use Xilinx VHDL module for simulation of Encoder.

Efficient Implementation of Scalar Multiplication for Elliptic Curve Cryptography using Ancient Indian Vedic Mathematics over GF(p)

Elliptic Curve Cryptography (ECC) is one of the safest standard algorithms, based on public-key, for providing the security in communication and networks. One of the most time consuming processes in ECC algorithm for encryption/decryption is the scalar multiplication, i.e., KP, where P is the text which is on the elliptic curve. This paper examines that computation can be speeded up by using Ancient Indian Vedic Mathematics. Coding is done using Verilog-HDL and downloaded on target device as Virtex 5. Our proposed work is six times faster than the previous work when applied in point doubling using Spartan3 as target device.

Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design

A typical processor central processing unit devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. In this paper, comparative study of different multipliers is done for low power requirement and high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e. “Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.

High Speed Vedic Multiplier for Digital Signal Processors

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among the various methods of multiplications in Vedic mathematics, Urdhva tiryakbhyam is discussed in detail. Urdhva tiryakbhyam is a general multiplication formula applicable to all cases of multiplication. This algorithm is applied to digital arithmetic and multiplier architecture is formulated. This is a highly modular design in which smaller blocks can be used to build higher blocks. The coding is done in VHDL (very high speed integrated circuits hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the modified Booth Wallace multiplier which is a fast multiplier. This Vedic multiplier can bring about great improvement in DSP performance.