Analysis Of Single Event Transients Research Articles

Analysis of Single Event Transients in Arbitrary Waveforms Using Statistical Window Analysis

Window or taper functions are commonly used in data processing to detect transient events or for time-averaging of frequency spectra. A generalized window function is demonstrated using the Ionizing Radiation Effects Spectroscopy (IRES) technique to enhance the measurement of transient anomalies within arbitrary waveforms. The IRES filter is used to convolve time data with a sliding window consisting of a moment-generating function. The resulting time-dependent statistical moments can be used to eliminate any steady-state signatures, including noise, and extract transient behaviors. The IRES filter is used to analyze data from heavy-ion exposures of commercial off-the-shelf (COTS) operational amplifiers, laser-induced transients in CMOS phase-locked loops, and simulated transients in digital and analog circuits. The performance of the IRES filter in noisy environments shows that transients can be measured with higher fidelity than standard amplitude thresholding. This statistical window analysis technique may remove the need for complex triggering mechanisms on instrumentation and does not require <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a-priori</i> knowledge of transient characteristics. Potential applications of IRES include real-time measurement, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> data analysis, and machine learning.

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs

Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden core of many applications especially in space and avionic fields where reliability is an important concern. In particular, for Flash-based FPGAs, when adopted in those applications, the main concern is radiation-induced voltage glitches known as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool is presented for evaluating the sensitivity of the implemented circuit regarding SET and mitigating this effect. This tool has been applied to EUCLID space mission project including more than ten modules. The experimental results demonstrate the efficiency of the proposed tool.

Single event transients monitoring and diagnostic in FPGA

Analysis of single event transients (SETs) generated in field programmable gate arrays (FPGA) under heavy charged particles (HCP) irradiation and SET suppression methods is performed. The circuit for FPGA SET detection is designed for transients generated both inside FPGA and outside at package pin level. SET registration inside FPGA is carried out as an event when logical cell is switched. The SET control schematic circuit efficiency has been comparatively verified using heavy ion accelerator and picosecond focused laser source. SET in FPGA experimental results are presented and discussed.

Cascaded Propagation and Reduction Techniques for Fault Binary Decision Diagram in Single-event Transient Analysis

Cascaded Propagation and Reduction Techniques for Fault Binary Decision Diagram in Single-event Transient Analysis

A Practical Approach to Single Event Transient Analysis for Highly Complex Design

Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow.

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phase-locked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.

Single event transient analysis of an SOI operational amplifier for use in low-temperature Martian exploration

The next generation of Martian rovers to be launched by Jet Propulsion Laboratory (JPL) are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-on-insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shown to be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xe beams of energy 25 MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36 MeV O 6+ microbeam at the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern.

A New Approach to the Analysis of Single Event Transients in VLSI Circuits

Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of SETs via zero-delay simulation instead of timed simulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time. Moreover, circuits enriched with time-related information are suitable for hardware emulation thus allowing further reducing the time for SET-effect analysis, while providing the same accuracy of state-of-the-art approaches based on timed simulations. The paper reports results showing how the proposed method can be effectively used to analyze complex designs.

Applicability of circuit macromodeling to analog single-event transient analysis

We have evaluated the applicability of vendor-supplied analog circuit macromodels to single-event transient (SET) analyses. Our findings demonstrate that macromodeling is very effective for system-level SET investigations; yet it is inadequate to address details of SET initiation at the IC level. Study of both dc and transient applications show that the circuitry peripheral to the ion strike location can be macromodeled and still retain an excellent ability to accurately transmit propagating voltage transients.

Efficient analysis of single event transients

The effects of charged particles striking VLSI circuits and producing single event transients (SETs) are becoming an issue for designers who exploit deep sub-micron technologies; efficient and accurate techniques for assessing their impact on VLSI designs are thus needed. This paper presents a new approach for generating the list of faults to be addressed during fault injection experiments tackling SET effects, which resorts to static timing analysis. Moreover, it proposes a simplified SET fault model, which is suitable for being adopted within a zero-delay fault simulation tool. Experimental results are reported on both standard benchmarks and real-life circuits assessing the effectiveness of the proposed techniques.