Analysis Of Large Analog Circuits Research Articles

Hierarchical approach to exact symbolic analysis of large analog circuits

This paper proposes a novel approach to the exact symbolic analysis of very large analog circuits. The new method is based on determinant decision diagrams (DDDs) representing symbolic product terms. But instead of constructing DDD graphs directly from a flat circuit matrix, the new method constructs DDD graphs in a hierarchical way based on hierarchically defined circuit structures. The resulting algorithm can analyze much larger analog circuits exactly than before. The authors show that exact symbolic expressions of a circuit are cancellation-free expressions when the circuit is analyzed hierarchically. With this, the authors propose a novel symbolic decancellation process, which essentially leads to the hierarchical DDD graph constructions. The new algorithm partially avoids the exponential DDD construction time by employing more efficient DDD graph operations during the hierarchical construction. The experimental results show that very large analog circuits, which cannot be analyzed exactly before like /spl mu/A725 and other unstructured circuits up to 100 nodes, can be analyzed by the new approach for the first time. The new approach significantly improves the exact symbolic capacity and promises huge potentials for the applications of exact symbolic analysis.

Canonical symbolic analysis of large analog circuits with determinant decision diagrams

Symbolic analysis has many applications in the design of analog circuits. Existing approaches rely on two forms of symbolic-expression representation: expanded sum-of-product form and arbitrarily nested form. Expanded form suffers the problem that the number of product terms grows exponentially with the size of a circuit. Nested form is neither canonical nor amenable to symbolic manipulation. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph-called a determinant decision diagram (DDD)-and performing symbolic analysis by graph manipulations. We show that DDD construction, as well as many symbolic analysis algorithms, takes time almost linear in the number of DDD vertices. We describe an efficient DDD-vertex ordering heuristic and prove that it is optimum for ladder-structured circuits. For practical analog circuits, the numbers of DDD vertices are several orders of magnitude less than the numbers of product terms. The algorithms have been implemented and compared respectively to symbolic analyzers ISAAC and Maple-V in generating the expanded sum-of-product expressions, and SCAPP in generating the nested sequences of expressions.

Symbolic analysis of large analog circuits using a sensitivity-driven enumeration of common spanning trees

A new approach for the generation of approximate symbolic network functions is presented. This approach is used to analyze large analog integrated circuits. It is based on a matroid intersection algorithm that directly enumerates common spanning trees of a two-graph representation of a given circuit. The approximation algorithm is based on an inspection of the sensitivity of the magnitude of a network function with respect to the different coefficients of a network function. These sensitivities as a function of frequency control the enumeration process. In this way, the algorithm enumerates a minimum number of the dominant terms for each coefficient of the network function The complete algorithm runs in O(Kmn/sup 3/) time, in which K is the average number of matroid intersections that must be generated for the approximation of each coefficient of the network function, n is the number of nodes in the linearized network and m the number of circuit elements. At the end of the paper experimental results are presented. These results indicate that this new approach is superior to other approaches to generate an approximate symbolic network function from a given two-graph.

Efficient approximation of symbolic network functions using matroid intersection algorithms

An efficient and effective approximation strategy is crucial to the success of symbolic analysis of large analog circuits. In this paper we propose a new approximation strategy for the symbolic analysis of linear circuits in the complex frequency domain. The strategy directly generates common spanning trees of a two-graph in decreasing order of tree admittance product, using matroid intersection algorithms. The strategy reduces the total time for computing an approximate symbolic expression in expanded format to polynomial with respect to the circuit size under the assumption that the number of product terms retained in the final expression is polynomial. Experimental results are clearly superior to those reported in previous works.