Analog-to-digital Converters Error Research Articles

Hardware design implementation issues of the estimator-based controller using FPGA

ABSTRACTHardware implementation issues play a vital role to realize the system accurately. Realization of hardware in digital domain has more advantages than analog domain. Field programming gate array (FPGA) based architectures are suitable for fast and reconfigurable systems. In this paper, implementation issues of an estimator based controller using FPGA are discussed. Verilog coding is developed to defeat these issues and efficient hardware mapping is derived. Input signal processing is proposed to overcome the analog to digital converter (ADC) interfacing issues such as quantization, sampling rate, resolution, non-linearity error and offset error. Optimum bit sizing of digital control modules are derived, considering system requirements and specifications. Controller operations are analyzed in binary form to choose the bit size of various operands and control modules, to derive accurate results. In this application, a 16-bit control architecture is proposed to estimate states of the converter and to generate control signals. Estimator based controller is designed for a dc-dc converter. Atlys Spartan-6 XC6SLX45 FPGA is used to implement the controller. Implementation issues such as ADC errors, settling time, the bit size of variables, quantization effects of the estimator and controller are mainly focused. It enables verilog coding quite easier to implement non-linear controllers using FPGA.

A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning

This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ADC. The proposed ADC integrates a stochastic flash ADC (SF-ADC) into a successive approximation register ADC (SAR-ADC) to enhance its resolution. The SF-ADC is also used as a digitally controlled variable threshold comparator to provide error correction of the SAR-ADC. The proposed system also calibrates the ADC error using the machine learning algorithm on an external PC without additional power dissipation at a sensor node. Due to the flexibility of the system, the design complexity of an AFE IC can be relaxed by using these techniques. The target resolution is 18 bits, and the target bandwidth (without digital low-pass filter) is about 5 kHz to deal with several types of biopotential signals. The design is fabricated in a 130-nm CMOS process and operates at 1.2-V supply. The fabricated ADC achieves the SNDR of 88 dB at a sampling frequency of 250 kHz by using the proposed calibration techniques. Due to the high-resolution ADC, the input-referred noise is 2.52 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> with a gain of 28.5 dB.

Effect and compensation of ADC nonlinearity on magnetic accommodation measurements

In this paper we analyze how static errors of Analog-to-Digital converters (ADCs) can influence the measurement of magnetic accommodation in soft ferrite core. In a first analysis, the discussion is carried out through a series of simulated ADC INLs applied to simulated signals and experimental data. Possible impacts of the integral nonlinearity (INL) on the reconstruction of the B−H trajectory are shown. In a second phase, a real ADC INL is considered to better quantify the impact of real ADC errors on the measurements. An easy to implement procedure based on physical symmetry property of the material is presented and adopted to reduce the INL effect on magnetic accommodation measurements. Finally, a comparison between the proposed approach and a mid-point linearization compensation technique of INL is reported showing the validity of the presented procedure.

Correction of ADC Errors by Additive Iterative Method with Dithering

The iterative method could be used for automatic accuracy improvement of a measurement system. In its application for analogto-digital converter (ADC) a quantization error represents a limitation for the correction process. Therefore, combination of correction methods is common for ADC error correction. Combination of the additive iterative method (AIM) with nonsubtractive dithering (ND) has been proposed for slow measurement based on ADC where errors could change in time. The principle of combination of both techniques is described in the paper. AIM is based on precise inverse element (IE). In the designed system the IE output signal is created by pulse width modulation and low-pass filtering. A technique similar to deterministic dithering is employed to achieve precise processing of signal from IE. Analysis of influence of stochastic dither upon the results of correction is performed with the aim to find optimal parameters of ND. Finally, dependency of the root mean squared error and error dispersion on the measured value is drawn to show how AIM corrects the nonlinear deterministic error but slightly increases system noise.

“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

The ldquosplit analog-to-digital converter (ADC)rdquo architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> interleaved ADCs requires 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> + 1 half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.

Bayesian Calibration of a Lookup Table for ADC Error Correction

This paper presents a new method for the correction of nonlinearity errors in analog-to-digital converters (ADCs). The method has been designed to allow a self-calibration in systems where an internal signal can be generated, such as base stations for mobile communications. The method has been implemented and tested in simulation on the behavioral model of commercial ADCs and on a hardware setup composed by a data acquisition board and a distorting circuit

Digital Background Correction of Harmonic Distortion in Pipelined ADCs

Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in high-accuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs

Improved Determination of the Best Fitting Sine Wave in ADC Testing

The sine wave test of an analog-to-digital converter (ADC) means to excite the ADC with a pure sine wave, look for the sine wave which best fits the output in least squares (LS) sense, and analyze the difference. This is described in the IEEE standards 1241-2000 and 1057-1994. Least squares is the "best" fitting method most of us can imagine, and it yields very good results indeed. Its known properties are achieved when the error (the deviation of the samples from the true sine wave) is random, white (the error samples are all independent), with zero mean Gaussian distribution. Then, the LS fit coincides with the maximum likelihood estimate of the parameters. However, in sine wave testing of ADCs, these assumptions are far from being true. The quantization error is partly deterministic, and the sample values are strongly interdependent. For sine waves covering less than, say, 20 quantum levels, this makes the sine wave fit worse than expected, and since small changes in the sine wave affect the residuals significantly, especially close to the peaks, ADC error analysis may become misleading. Processing of the residuals [e.g., the calculation of the effective number of bits, (ENOB)] can exhibit serious errors. This paper describes this phenomenon, analyzes its consequences, and suggests modified processing of samples and residuals to reduce the errors to negligible level.

A State of the Art on ADC Error Compensation Methods

Analog-to-digital converters (ADCs) are critical components of signal-processing systems. ADC errors can compromise the overall accuracy and the effectiveness of the whole system. This leads researchers to direct increasing attention to error correction topics. In this paper, some ADC error compensation methods are briefly introduced according to a classification criterion based on the main research trends.

Optimal index-bit allocation for dynamic post-correction of analog-to-digital converters

Signal processing methods for digital post-correction of analog-to-digital converters (ADCs) are considered. ADC errors are in general signal dependent, and in addition, they often exhibit dynamic dependence. A novel dynamic post-correction scheme based on look-up tables is proposed. In order to reduce the table size and, thus, the hardware requirements, bit-masking is introduced. This is to limit the length of the table index by deselecting index bits. At this point, the problem of which bits to use arises. A mathematical analysis tool is derived, enabling the allocation of index bits to be analyzed. This analysis tool is applied in two optimization problems, optimizing the total harmonic distortion and the signal-to-noise and distortion ratio, respectively, of a corrected ADC. The correction scheme and the optimization problems are illustrated and exemplified using experimental ADC data. The results show that the proposed correction scheme improves the performance of the ADC. They also indicate that the allocation of index bits has a significant impact on the ADC performance, motivating the analysis tool. Finally, the optimization results show that performance improvements compared with static look-up table correction can be achieved, even at a comparable table size.

Volterra filtering for integrating ADC error correction, based on an a priori error model

Dynamic nonlinear effects contribute significantly to analog-to-digital converters (ADCs) distortion. Volterra filtering can present an effective method for modeling and compensation of these phenomena. Considering an a priori error model of ADC allows us to find an efficient inverse Volterra model for error correction. The method's effectiveness is demonstrated by experimental measurements.

Digital cancellation of D/A converter noise in pipelined A/D converters

Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs), The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. The technique continuously measures and cancels the portion of the ADC error arising from DAC noise during normal operation of the ADC, so no special calibration signal or auto-calibration phase is required. The details of the technique are described in the context of a nominal 14-bit pipelined ADC example at both the signal processing and register transfer levels. Through this example, the paper demonstrates that in the presence of realistic component matching limitations the technique can improve the overall ADC accuracy by several bits with only moderate digital hardware complexity.

ADC compensation using a sinewave histogram method

The need for high dynamic range analog to digital converters (ADCs) is strong due to the growing use of digital signal processing in communications applications. ADC performance has improved over the years due to advances in both design concepts and semiconductor technologies. However most ADCs still still exhibit undesirable distortion in addition to quantization error, thus limiting spurious free dynamic range, (SFDR), in digital receiver applications. This paper describes a new method for developing ADC error function models using standard sinewave histogram methods. The method provides better error representation by providing error basis functions for every state. Results show this method is capable of removing all slope dependent errors in complex ADC error models and application to a 200 MSPS ADC showed more than 10 dB improvement in SFDR over the full Nyquist band for the ADC.

Static testing of ADCS using wavelet transforms

Almost all analog signal processing is being replaced by digital signal processing techniques in today's communication networks, as well as in other applications. This means that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which serve as the interfaces between the analog and the digital worlds, will together share a growing influence on overall system performance. In this paper, we present a new method, based on wavelet transforms, for measuring ADC errors, namely nonlinearity, gain error, and offset error. Unlike the traditional DNL method, this new method, which we have called NSR, for noise-to-signal ratio estimated in amplitude-scale plane, can be used during circuit design, production testing, and in service testing of ADCs and DACs.

Testing an ADC linearized with pseudorandom dither

When a pure sinewave is digitized by an analog-to-digital converter (ADC), the errors are determined by the input voltage and, hence, the phase of the sinewave. The errors generate signal harmonics coherently. One technique used to reduce the harmonic distortion is dithering by combining a pseudorandom wide bandwidth dither signal with the input signal. When pseudorandom dither is added to a sinusoidal signal, it randomizes the ADC errors with respect to the sinewave so that the errors cannot add coherently. The dominant effect of the dither component is to reduce large spurious harmonic distortion components by spreading them into many smaller ones. This paper presents a test method for testing an ADC linearized with pseudorandom dither. We present results of testing a 12-bit, 5 MHz converter and a state-of-the-art, 14-15-bit, 10 MHz converter.

A new approach for estimating high-speed analog-to-digital converter error

One of the most significant types of error in digital signal processing (DSP) systems working with wideband signals is the error introduced by the analog-to-digital converter (ADC). This paper investigates an accurate, simple, and low-cost method, which can be used for calibrating, testing, and quick-monitoring ADC. The proposed method analyzes the deviation of a value of the converted signal, which is similar to the ADC working signal, from its true value. The deviation represents the tested ADC error evaluated for both frequency and voltage ranges of ADC operations using statistical data processing. It gives the only necessary ADC accuracy characteristic to a user leaving the rest to the designer. Comparisons between the proposed ADC testing approach and the known techniques are provided. The errors incurred by the method are analyzed. A special source of random signal with controlled statistical parameters and its calibration technique are also described.

Nonlinear Effects of Digitizer Errors in FT-IR Spectroscopy

This paper is an investigation of the effects of errors in the analog-to-digital converter (ADC) of a Fourier transform infrared (FT-IR) spectrometer on the photometric accuracy of that spectrometer. The effect of ADC errors on the spectrum after Fourier transformation is calculated analytically for monochromatic, two-line, and wide square band emission spectra. Numerical modeling is used to extend the analysis to absorption spectra, and to include the effects of noise on the amplitude of absorbance bands. These analyses showed that ADC errors can generate artifacts throughout the spectrum, although the largest effects occur at sharp spectral features. Errors as large as 8% in the amplitude of absorbance bands can be produced by ADC errors of one least significant bit (LSB), in a 15-bit ADC. These results were confirmed qualitatively by measuring the net height of the oxygen vibrational band in silicon at 1107 cm−1 using four different ADC circuit boards in the same FT-IR spectrometer. At the highest signal levels, the ADCs disagreed by as much as 4%, even though their static transfer characteristics (which were measured in a separate experiment) exhibited errors of less than ±2 LSBs.