Analog-to-digital Converters Bits Research Articles

Channel estimation and MIMO combining architecture in millimeter wave cellular system with few ADC bits

Hybrid combiner and precoder architectures, radio frequency (RF) chain, analog phase shifters, digital-to-analog converter (DAC), and analog-to-digital converter (ADC) are components of a millimeter wave cellular system. Prior works in the area of millimeter wave cellular system design employ receiver with infinite bit and large amount of RF chain that scales linearly with the quantity of transmitting and receiving antennas. This mode of design no doubt increases power demand or requirement of a typical millimeter wave system. In this work, hybrid architecture with few RF chains and small number of ADC bits are proposed and are used as candidate for millimeter wave channel estimation and cellular communication. In that connection, least square (LS), orthogonal matching pursuit (OMP), compressed sampling matching pursuit (CoSAMP), and deep learning (DL) techniques are utilized for analytical investigation. Indeed, computational results reveal that, when ADC consisting of uniform mid- rise quantizer is employed, the performance of 4 and 6 bits at signal-to-noise ratio (SNR) values of − 10 dB and 20 dB is at par with infinite bit (unquantized case). As a validation, DL compares favorably well with adaptive compressed sensing (ACS) technique previously used in the literature for channel estimation, while OMP and CoSAMP show better performance than ACS.

SAMBA: Sparsity Aware In-Memory Computing Based Machine Learning Accelerator

Machine Learning (ML) inference is typically dominated by highly data-intensive Matrix Vector Multiplication (MVM) computations that may be constrained by the memory bottleneck due to massive data movement between processor and memory units. Although analog in-memory computing (IMC) ML accelerators have been proposed to execute MVM with high efficiency, the latency and energy of such analog computing systems can be dominated by the large latency and energy costs from analog-to-digital converters (ADC). Leveraging sparsity in ML workloads, reconfigurable ADCs can improve the MVM energy and latency by reducing the required ADC bit precision. However, such improvement in latency can be hindered by non-uniform sparsity of the weight matrices mapped into hardware. Moreover, data movement between MVM processing cores may become another factor that delays the overall system-level performance. To address these issues, we propose SAMBA, Sparsity Aware IMC Based Machine Learning Accelerator. First, we propose load balancing at the mapping of weight matrices into physical crossbars. The goal of load balancing is to accommodate reconfigurable ADCs and address the possible delay of MVM processing caused by non-uniform sparsity in the weight matrices. Second, we propose optimizations in arranging and scheduling the tiled MVM hardware to minimize the overhead of data movement across multiple processing cores. Our evaluations show that the proposed load balancing technique can achieve performance improvement by eliminating the non-uniformity in the sparsity of mapped matrices. Moreover, we demonstrate that data movement optimizations can further improve both performance and energy efficiency regardless of sparsity condition. With the combination of load balancing and data movement optimization in conjunction with reconfigurable ADCs, our proposed approach provides up to 2.38x speed-up and 1.54x energy efficiency over state-of-art analog IMC based ML accelerators for ImageNet datasets on Resnet-50 architecture.

Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators

In Analog Computing-in-Memory (CIM) neural network accelerators, analog-to-digital converters (ADCs) are required to convert the analog partial sums generated from a CIM array to digital values. The overhead from ADCs substantially degrades the energy efficiency of CIM accelerators so that previous works attempted to lower the ADC resolution considering the distribution of the partial sums. Despite the efforts, the required ADC resolution still remains relatively high. In this article, we propose the data-driven partial sum quantization scheme, which exhaustively searches for the optimal quantization range with little computational burden. We also report that analyzing the characteristics of the partial sum distributions at each layer gives an additional information to further reduce the ADC resolution compared to previous works that mostly used the characteristics of the partial sum distributions of the entire network. Based on the finer-level data-driven approach combined with retraining, we present a methodology for extreme partial-sum quantization. Experimental results show that the proposed method can reduce the ADC resolution to 2 to 3 bits for CIFAR-10 dataset, which is the smaller ADC bit resolution than any previous CIM-based NN accelerators.

Photonics-Assisted Millimeter-Wave Communication System Based on Low-Bit Gaussian Mixture Model Adaptive Vector Quantization

The quantization technique with a low-bit resolution can significantly reduce the cost and power consumption of analog-to-digital converter (ADC). It will play an important role in energy conservation and cost reduction for the incoming B5G millimeter-wave (MMW) communication systems. In this paper, we propose and demonstrated experimentally a low-bit Gaussian mixture model (GMM) based non-uniform adaptive vector quantization (AVQ) scheme for the low-cost intensity modulated envelope detection photonics-assisted 28 GHz MMW communication system for the first time. The principles of GMM-based one-dimensional adaptive scalar quantization (ASQ) and multi-dimensional AVQ are first introduced, and then are used to realize the low-bit non-uniform adaptive quantization for reducing the ADC bit resolution of MMW receiver. Furthermore, the performance of traditional uniform quantization, the present <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> -means and proposed GMM-based non-uniform ASQ/AVQ schemes are evaluated and compared in detail. Utilizing the proposed GMM-based AVQ scheme, the ADC quantization resolution in our MMW receiver can be reduced from 5 bits of the traditional uniform quantization to as low as 2 bits, without noticeable performance penalty. Moreover, as compared with the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> -means-based quantization scheme, the MMW receiver enabled by GMM-based ASQ/AVQ scheme can save about half of the quantization time under similar performance. This is mainly because the clustering based on probability converges faster than the Euclidean distance, which significantly reduces the number of iterations required. Therefore, the GMM-based AVQ scheme is a promising solution to realize high performance ADCs with low-bit resolution for future MMW-enabled optical fiber wireless access networks.

Spectral efficiency for IRS-assisted uplink mmWave massive MISO systems with low-resolution ADCs

In this paper, we investigate the uplink achievable spectral efficiency (SE) for an intelligent reflecting surface (IRS)-assisted millimeter wave (mmWave) multiple-input single-output (MISO) system, where all antennas at the BS are equipped with cheaper low-resolution analog-to-digital converters (ADCs) and an IRS adjusts its reflecting phase shifts to facilitate information transfer. To maximize the uplink achievable SE, we design the phase shift of each reflecting element and obtained the optimal phase shift matrix in the terms of the statistical channel state information (CSI). An theoretical expression of the uplink achievable SE of massive MISO system is obtained with the zero forcing (ZF) detector is derived. Based on this derived theoretical result, the behaviors of the achievable SE with respect to several physical parameters are revealed that includes the number of antennas, the transmit power, the number of reflecting elements, and the quantization bits of the low-resolution ADCs. Finally, we provide the numerical results by Monte Carlo simulation to verify that our theoretical analysis is accurate. Results show that the achievable SE increases with the number of antennas, the number of quantization bits of the ADC and the reflecting elements of the IRS, but tends to a saturation rate. In addition, we find that the SE inevitably suffers a certain loss due to the phase shift noise is unavoidable and the quantization accuracy of IRS, which can be compensated by increasing the transmit power and the number of reflecting elements.

Active device detection and performance analysis of massive non-orthogonal transmissions in cellular Internet of Things

This paper investigates multiple access schemes for uplink and downlink transmissions in cellular networks with massive Internet of Things (IoT) devices. Recall that single-carrier frequency division multiple access and orthogonal frequency division multiple access, which are orthogonal multiple access (OMA) schemes, have been conventionally adopted for uplink and downlink transmissions in narrow-band IoT, respectively. Unlike these OMA schemes, we propose two non-orthogonal multiple access (NOMA) schemes for cellular IoT with short-packet transmissions. Especially, a generalized expectation consistent signal recovery-based algorithm is proposed to estimate active devices, channel state information and data in uplink transmission, where all of the active devices are allowed to transmit their pilots and data through the same resource block without authorization. On the other hand, the active devices estimated during uplink transmission are grouped for downlink transmission with a trade-off between performance and detection complexity. Additionally, the data error rates are analysed for both uplink and downlink transmissions with low-resolution analog-to-digital converters (ADCs), where the effects of critical parameters such as the estimation error, ADC bits, packet length, and message bits are revealed. Both simulation and analytical results are provided to demonstrate the excellent performance of the proposed NOMA schemes and algorithms, especially for active device, channel, and data estimations. More importantly, the obtained results show that the data error rate performance of downlink NOMA is superior to that of OMA when the message bits of devices in one group are selected following the proposed strategy.

Influence of Analog-To-Digital Conversion and Decimation Parameters on the Signal-To-Noise Ratio in the Radar Path

Introduction. The digital representation of received radar signals has provided a wide range of opportunities for their processing. However, the used hardware and software impose some limits on the number of bits and sampling rate of the signal at all conversion and processing stages. These limitations lead to a decrease in the signal-to-interference ratio due to quantization noise introduced by powerful components comprising the received signal (interfering reflections; active noise interference), as well as the attenuation of a low-power reflected signal represented by a limited number of bits. In practice, the amplitude of interfering reflections can exceed that of the signal reflected from the target by a factor of thousands.Aim. In this connection, it is essential to take into account the effect of quantization noise on the signal-tointerference ratio.Materials and methods. The article presents expressions for calculating the power and power spectral density (PSD) of quantization noise, which take into account the value of the least significant bit of an analog-to-digital converter (ADC) and the signal sampling rate. These expressions are verified by simulating 4-, 8- and 16-bit ADCs in the Mathcad environment.Results. Expressions are derived for calculating the quantization noise PSD of interfering reflections, which allows the PSD to be taken into account in the signal-to-interference ratio at the output of the processing chain. In addition, a comparison of decimation options (by discarding and averaging samples) is performed drawing on the estimates of the noise PSD and the signal-to-noise ratio.Conclusion. Recommendations regarding the ADC bit depth and sampling rate for the radar receiver are presented.

Spectrum and energy efficient kalman‐based hybrid combiner for mmWave massive MIMO systems

The hybrid beamforming can significantly improve the spectral and energy efficiencies of the millimeter-wave (mmWave) massive multiple input multiple output (MIMO) systems without obvious performance loss. However, the fundamental limitation of existing hybrid beamforming is that they include high-resolution analog-to-digital converters (ADCs) which consume high power. To overcome this fundamental limitation, in this paper, spectrum and energy efficient mmWave massive MIMO transmission scheme is proposed that jointly optimizes the hybrid combiner and the number of ADC bits. Particularly, the hybrid combiner is presented as a combination of three parts: the analog combiner matrix, the quantization matrix, and the digital baseband matrix which is based on the Kalman filter. Unlike most existing works that rely on sumrate optimization to design the hybrid combiner, in this work, the mean square error (MSE) is chosen as the main performance metric to describe the reliability of the system. Simulations results confirm that the proposed Kalman based hybrid combiner exhibits the best performance in terms of spectral and energy efficiencies compared to minimum mean square error (MMSE) and zero forcing (ZF) receivers.

Optimal Per-Antenna ADC Bit Allocation in Correlated and Cell-Free Massive MIMO

In Massive MIMO base stations (BSs), the hardware design needs to balance high spectral efficiency (SE) with low complexity. The level of hardware impairments (HWIs) indicates how strong the signal distortion introduced by hardware imperfections is. In particular, the analog-to-digital converters (ADCs) have an important impact on signal distortion and power consumption. This article addresses the fundamental problem of selecting the optimal hardware quality in the Massive MIMO space. In particular, we examine the optimal HWI and ADC bit allocation per BS antenna to maximize the SE. The results show that in co-located arrays with low channel gain variations across antennas, equal ADC bit allocation is optimal. In contrast, cell-free Massive MIMO systems benefit the most from optimizing the ADC bit allocation achieving improvements in the order of 2 [bit-per-channel-use] per user equipment when using regularized zero-forcing (RZF). In addition, when including the impact of power consumption in cell-free Massive MIMO with RZF, allocating low values of mixed ADC bit resolutions across the BS antennas can increase the energy efficiency up to 30% compared to equal ADC bit allocation.

Performance Analysis of Massive MIMO Relay Systems With Variable-Resolution ADCs/DACs Over Spatially Correlated Channels

The use of low-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) is recognized as a practical technique to reduce power consumption and hardware cost for massive multiple-input and multiple-output (MIMO) systems. In this context, by leveraging on the additive quantization noise model (AQNM), this paper investigates the performance of massive MIMO relay systems with a variable-resolution ADC/DAC-based architecture, where each ADC and DAC use arbitrary bits for quantization. To be specific, we first derive the closed-form expression of achievable rate over spatially correlated Rayleigh fading channels by using perfect channel state information (CSI), maximal ratio combining (MRC), and maximal ratio transmission (MRT). Afterwards, we extend the work to the case of imperfect CSI. The analytical expressions reveal some insights of key parameters, i.e., spatial channel correlation, large-scale fading coefficients, estimate errors, and the resolution of ADCs/DACs. Finally, simulation results validate our theoretical analyses and confirm that the achievable rate reduces as the spatial correlation rises. Besides, we provide the condition under which coarse DACs (ADCs) and receive spatial correlation (transmit spatial correlation) dominate the loss of achievable rate. Moreover, provided that the total number of quantization bits is constant, we find that the achievable rate is optimal over spatially correlated channels when all ADC and DAC adopt the same quantization bits from the perspective of statistic.

Advanced Receiver Architectures for Millimeter-Wave Communications with Low-Resolution ADCs

Employing low-resolution analog-to-digital converters (ADCs) for millimeter-wave receivers with large antenna arrays provides an opportunity to efficiently reduce power consumption of the receiver. Reducing ADC resolution, however, results in performance degradation due to non-negligible quantization error. In addition, the large number of radio frequency chains is still not desirable. Accordingly, conventional low-resolution ADC systems require more efficient designs to minimize the cost and complexity while maximizing performance. In this article, we discuss advanced low-resolution ADC receiver architectures that further improve the spectral and energy efficiency trade-off. To reduce both the numbers of RF chains and ADC bits, hybrid analog and digital beamforming is jointly considered with low-resolution ADCs. We explore the challenges in designing such receivers and present key insights on how the advanced architectures overcome such challenges. As alternative low-resolution ADC receivers, we also introduce receivers with learning-based detection. The receiver does not require explicit channel estimation, and thus is suitable for one-bit ADC systems. Finally, future challenges and research issues are discussed.

Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. This paper gives a detailed analysis for the reasons of poor linearity for passive-charge-sharing SAR ADCs and proposes solutions. The proposed ADC architecture with one-reference-cap-per-bit and short switches addresses the issue of signal-dependent reference voltage droop during SAR ADC bit trials and orthogonalizes the bit weights. The calibration technique presented further calibrates the ADC to 16-bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the digital-to-analog converter (DAC) capacitor array, the first reported in this type of SAR ADC. This paper provides the foundation of building a precision SAR ADC out of on-chip reference capacitors. Measurement result from a prototype test chip shows ±0.8 LSB (16-bit level) integrated non-linearity at 1 MSPS.

A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s

This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental $\Sigma \Delta $ digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit $\Sigma \Delta $ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available $\Sigma \Delta $ DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80-kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 $\mu \text{W}$ . In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth.

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.

Optical-analog-to-digital conversion based on successive-like approximations in octagonal-shape photonic crystal ring resonators

Implementing intensity-dependent Kerr-like nonlinearity in octagonal-shape photonic crystal ring resonators (OSPCRRs), a new class of optical analog-to-digital converters (ADCs) with low power consumption is presented. Due to its size dependent refractive index, Silicon (Si) nanocrystal is used as nonlinear medium in the proposed ADC. Coding system of optical ADC is based on successive-like approximations which requires only one quantization level to represent each single bit, despite of conventional ADCs that require at least two distinct levels for each bit. Each is representing bit of optical ADC is formed by vertically alignment of double rings of OSPCRRs (DR-OSPCRR) and cascading m number of DR-OSPCRR, forms an m bit ADC. Investigating different parameters of DR-OSPCRR such as refractive indices of rings, lattice refractive index, and coupling coefficients of waveguide-to-ring and ring-to-ring, the ADC's threshold power is tuned. Increasing the number of bits of ADC, increases the overall power consumption of ADC. One can arrange to have any number of bits for this ADC, as long as the power levels are treated carefully. Finite difference time domain (FDTD) in-house codes were used to evaluate the ADC's effectiveness.

Evaluation of logarithmic vs. linear ADCs for neural signal acquisition and reconstruction.

An evaluation of the effectiveness of logarithmic quantization for neural signals is performed in this paper. Logarithmic analog to digital converters (ADCs) are employed in biomedical applications where signals with high dynamic range are recorded. For the same number of bits of a linear ADC, a logarithmic one can better resolve smaller signals, at a price of worse accuracy for high amplitudes. This feature can also reduce the number of bits required and then allow data reduction as well. No study was done to verify the efficacy of such ADCs on neural signals in the context of spike sorting. Using simulated and recorded publically available data this is done extensively in the paper. Neural signals are quantized with linear and logarithmic ADCs. Then using the original signal as reference, the new signals are processed with Osort for automated spike sorting. The results are compared with the reference to determine whether one of the two quantization methods provides some benefits. The result is that logarithmic ADCs outperform linear quantization only in the range from 2 to 5 bits. Such low resolutions are unfortunately not enough for proper spike sorting, hence logarithmic ADCs appear not to provide an improvement over a conventional ADC.

Hybrid Architectures With Few-Bit ADC Receivers: Achievable Rates and Energy-Rate Tradeoffs

Hybrid analog/digital architectures and receivers with low-resolution analog-to-digital converters (ADCs) are two low power solutions for wireless systems with large antenna arrays, such as millimeter wave and massive multiple-input multiple-output systems. Most prior work represents two extreme cases in which either a small number of radio frequency (RF) chains with full-resolution ADCs, or low-resolution ADC with a number of RF chains equal to the number of antennas is assumed. In this paper, a generalized hybrid architecture with a small number of RF chains and a finite number of ADC bits is proposed. For this architecture, achievable rates with channel inversion and singular value decomposition-based transmission methods are derived. Results show that the achievable rate is comparable to that obtained by full-precision ADC receivers at low and medium SNRs. A trade-off between the achievable rate and power consumption for the different numbers of bits and RF chains is devised. This enables us to draw some conclusions on the number of ADC bits needed to maximize the system energy efficiency. Numerical simulations show that coarse ADC quantization is optimal under various system configurations. This means that hybrid combining with coarse quantization achieves better energy-rate trade-off compared with both hybrid combining with full-resolutions ADCs and 1-bit ADC combining.

Digitally Controlled Analog Cancellation for Full Duplex Broadband Power Line Communications

Although in-band full-duplexing (IBFD) has long been implemented in various communication media, it was only recently that an IBFD solution was presented for broadband power line communications (BB-PLCs). The maximum attainable echo suppression using this solution is, however, limited by the dynamic range of the analog-to-digital converter (ADC). To counter this critical constraint, we propose echo cancellation in the analog domain, while persisting with a low-complexity frequency domain digital echo estimation. By formulating an expression for the number of ADC bits lost in IBFD over a conventional half-duplex operation, we show that the ADC dynamic range is no longer a limiting factor for our solution. We further extend our solution to present an analog cancellation method for multiple-input multiple-output IBFD BB-PLC systems. Finally, we present simulation results of echo cancellation and data rate gains obtained under realistic in-home BB-PLC settings, to demonstrate that our solution is capable of doubling bidirectional transfer rates in a large number of the tested network conditions.

Successive approximation-like 4-bit full-optical analog-to-digital converter based on Kerr-like nonlinear photonic crystal ring resonators

Implementing of photonic sampling and quantizing analog-to-digital converters (ADCs) enable us to extract a single binary word from optical signals without need for extra electronic assisting parts. This would enormously increase the sampling and quantizing time as well as decreasing the consumed power. To this end, based on the concept of successive approximation method, a 4-bit full-optical ADC that operates using the intensity-dependent Kerr-like nonlinearity in a two dimensional photonic crystal (2DPhC) platform is proposed. The Silicon (Si) nanocrystal is chosen because of the suitable nonlinear material characteristic. An optical limiter is used for the clamping and quantization of each successive levels that represent the ADC bits. In the proposal, an energy efficient optical ADC circuit is implemented by controlling the system parameters such as ring-to-waveguide coupling coefficients, the ring’s nonlinear refractive index, and the ring’s length. The performance of the ADC structure is verified by the simulation using finite difference time domain (FDTD) method.

Optimal Design of Secrecy Massive MIMO Amplify-and-Forward Relaying Systems With Double-Resolution ADCs Antenna Array

This paper focuses on a secrecy constrained massive multiple-input multiple-output (MIMO) relaying system in terms of the optimal design of system parameters such as the optimal total number of antennas at relay, where a more practical mixed analog-to-digital converters (ADCs) scheme, double-resolution ADCs scheme, is proposed. In the proposed double-resolution ADCs scheme, the total $M$ antennas at relay are divided into two parts, one of which includes $M_{0}$ antennas with medium-resolution ADCs only requiring 5~12 quantization bits and the remainder of which consists of $M_{1}$ antennas with low-resolution ADCs. The transmission from relay to destinations is exposed to a passive eavesdropper. For such massive MIMO relaying systems, we first derive the total achievable ergodic rates of legitimate users as well as the corresponding secrecy outage rates. Then, a reasonable energy consumption model is modeled so that the secrecy energy efficiency (SEE) is derived, where the effect of the source power, the resolutions of ADCs, and the ratio of the antenna numbers with medium- and low-resolution ADCs are exploited perfectly. The presented numerical results show that replacing high-resolution ADCs with medium-resolution ADCs is beneficial for improving the system SEE while the effect on the total achievable rate is very small. Specially, three main insights are achieved: 1) there exists an optimal value of the source power at which the SEE is optimal; 2) with given ratio $M_{0} :M_{1} $ , the optimal value of quantization bits of medium-resolution ADCs is upper-bounded, under which the system has higher SEE, that is to say, we obtain the upper bound of the resolution of the medium-resolution ADCs; and 3) the optimal number of the total antennas is impacted jointly by the number $b_{0}$ of the quantization bits of medium-resolution ADCs and the ratio $M_{0} :M_{1}$ . Specially, while the optimal number of the total antennas is 100 or so for the pure high-resolution ADCs systems, the one for the proposed double-resolution ADCs systems would up to 500~700. Moreover, the optimal antenna number is increasing with the decrease of $b_{0} $ and the ratio $M_{0} :M_{1} $ so that the system performance can be improved further.