Analog Routing Research Articles

Computational analysis of multi-contact phase change device for toggle logic operations

In this work, two dimensional six-contact phase change devices that can perform toggle logic operations is analyzed through 2D electrothermal simulations with dynamic materials modelling, integrated with CMOS access circuitry. Toggle configurations are achieved through a combination of isolation of some contacts from others using amorphous regions and coupling between different regions via thermal crosstalk. Use of thermal crosstalk as a coupling mechanism in a multi-contact device in the memory layer allows implementation of analog routing and digital logic operations at a significantly lower transistor count, with the added benefit of non-volatility. Simulation results show approximately linear improvement in peak current and voltage requirements with thickness scaling.

Analog Considerations for Designing a Potentiostat in a PSoC: Sources of Errors and Compensation Techniques

Designing with a Programmable System on a Chip (PSoC) allows for entire circuit designs to be implemented with a single commercially available chip and eliminates the need to physically assemble electronic components. This is possible as the PSoC incorporates a microcontroller with digital and analog components into a single package. While this design allows for much easier implementation of circuits, there are some drawbacks. In this paper we will demonstrate one of those drawbacks, high routing resistance in parts of the analog mesh that connects the analog parts and external pins. We show how this resistance can cause measurement errors when the PSoC is implemented as a single chip potentiostat. As the internal analog routing resistance is in the kΩ range, measuring currents in the Kॅ range can cause mV errors, leading to lose of voltage control during electrochemical experiments. We also demonstrate a calibration routine to compensate for this voltage error that reduced the error by over 90%.

Wire Load Oriented Analog Routing with Matching Constraints

As design complexity is increased exponentially, electronic design automation (EDA) tools are essential to reduce design efforts. However, the analog layout design has still been done manually for decades because it is a sensitive and error-prone task. Tool-generated layouts are still not well-accepted by analog designers due to the performance loss under non-ideal effects. Most previous works focus on adding more layout constraints on the analog placement. Routing the nets is thus considered as a trivial step that can be done by typical digital routing methodology, which is to use vias to connect every horizontal and vertical lines. Those extra vias will significantly increase the wire loads and degrade the circuit performance. Therefore, in this article, a wire load oriented analog routing methodology is proposed to reduce the number of layer changing of each routing net. Wire load is considered in the optimization goal as well as the wire length to keep the circuit performance after layout, while the analog layout constraints like symmetry and length matching are still satisfied during routing. As shown in the experimental results, this approach significantly reduces the wire load and performance loss after layout with little overhead on wire length.

A Fast Hierarchical Adaptive Analog Routing Algorithm Based on Integer Linear Programming

The shrinking design window and high parasitic sensitivity in advanced technologies have imposed special challenges on analog and radio frequency (RF) integrated circuit design. The state-of-the-art analog routing research tends to favor linear programming to achieve various analog constraints, which, although effective, fail to offer high routing efficiency on its own. In this article, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Our proposed method supports hierarchical routing, which can divide the entire routing area into multiple small heterogeneous regions where the ILP can efficiently derive routing solutions. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less-crowded routing region. For a large empty space, routing efficiency can be even boosted by creating more routing hierarchy levels. This scheme is especially beneficial to the analog and RF layouts, which are far sparser than their digital counterparts. The experimental results show that our proposed adaptive ILP-based router is much faster than the conventional ones, since it spends much less time in the areas that need no accurate routing anyway. The higher efficiency is demonstrated for large circuits and especially sparse layouts along with promising routing quality in terms of analog constraints.

DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths

With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order $ {\Sigma \Delta }$ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.

Nonuniform Multilevel Analog Routing With Matching Constraints

Symmetry, common-centroid, topology-matching, and length-matching constraints are four major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. Common-centroid constraints are also specified to route matched net symmetrically with respect to some common centers. Topology-matching constraints are commonly imposed on critical yet asymmetry nets with the same number of bends, vias, and wirelength. Length-matching constraints are specified to route the nets which have limited resources with the same wirelength. These four constraints can reduce current mismatches and unwanted electrical effects between two critical nets. In this paper, we propose the first work to simultaneously consider the four constraints for analog routing while minimizing total wirelength, bend numbers, via counts, and coupling noise at the same time. We first present a basic integer linear programming (ILP) formulation to simultaneously consider the four constraints for analog routing. Then, a prioritized-constraint-aware routing algorithm is proposed to assist analog designers for assigning the four matching constraints and optimizing routing topologies. Effective reduction techniques are also employed to reduce the numbers of ILP variables and constraints for the two routing algorithms. To further enhance the routing performance, a nonuniform multilevel routing framework is presented and integrated into our routing algorithms. Experimental results show that our approach can obtain better routing results and satisfy all specified routing constraints while optimizing circuit performance.

SIAR: Customized real-time interactive router for analog circuits

As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automatic analog routing is becoming more and more important. However, routing for analog circuits has always been an extremely challenging task due to complicated electrical and geometrical constraints. Due to these constraints, current analog routers often fail to obtain a routing solution that the designer wants. To incorporate the designer׳s expertise during routing, a customized real-time interactive analog router is attracting increasing concerns in industry.This paper presents a fast customized real-time interactive analog router called SIAR. A key feature of SIAR is that it allows for real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and SIAR will return and display the corresponding routing solution in real-time, such that the designer could choose the most satisfactory one. The guiding points are very important for the designer to obtain satisfactory routing solutions, even for routing solutions with analog matching constraints by setting symmetric guiding points. A new splitting graph based routing model is presented to efficiently search the routing path and record the number of turns/vias during searching by efficient tile splitting operations. SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. An efficient connecting point selection method is presented such that an optimal routing solution is preserved when connecting to a module. Different design rules such as variable wire and via width/spacing rules, along with the same-net spacing rules, are supported in SIAR. Moreover, a global routing stage is presented to speedup the routing process for large designs. Experimental results are promising.

Impact of Channel Estimation Errors and Power Allocation on Analog Network Coding and Routing in Two-Way Relaying

In this paper, we study two important transmission strategies in full-duplex two-way relaying in the presence of channel estimation errors. In analog network coding (ANC), the relay transmits the combined signals that were received from both sources, with the aim of achieving better spectral efficiency. However, due to imperfect channel-state information (CSI), sources cannot perfectly cancel their own data in the relayed signal. We derive an achievable information rate for ANC in imperfect-CSI conditions and show how the ANC performance can significantly be degraded as a result. Moreover, we derive cut-set bounds with channel estimation errors for traditional routing (TR), in which time sharing is used at the relay. Although it has been previously shown that ANC outperforms TR when the CSI is perfect, we find that it may not maintain its superiority in imperfect-CSI case at low signal-to-noise ratio (SNR) conditions. Next, we propose practical power allocation techniques that can be used in the sources and relay for both ANC and TR. The proposed power allocation schemes are relatively simple to compute and rely only on long-term channel statistics. Nevertheless, they are shown to be effective and close to optimal solutions for a wide range of SNRs, to different positions of the relay, and for both perfect- and imperfect-CSI conditions. By using the proposed power allocation techniques, it is possible to bring back advantages of ANC over TR for a wide range of SNRs in imperfect-CSI conditions.

Area routing for analog layout

An area router specifically tailored for the layout of analog circuits is presented. It is based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable cost function based on a set of user-defined weights. The weights can be automatically defined based on high-level electrical performance specifications and determine the net scheduling. An algorithm for symmetric routing preserves symmetries in differential architectures. Different current paths can be dealt with in each wire by means of a net partitioning procedure driven by information on the current driven by terminals. Shields can be built between critically coupled wires, in order to guarantee an effective limitation of cross-coupling. The weight-driven programmable cost function makes this router particularly suitable for a performance-driven approach to analog routing. Automatic weight definition also makes the use of the tool independent of the user's expertise. The implemented algorithms are described, and results proving the effectiveness of this approach are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

KOAN/ANAGRAM II: new tools for device-level analog placement and routing

The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A generalized approach to routing mixing analog and digital signal nets in a channel

A generalized algorithm for two-layer detailed channel routing of mixed analog and digital signal nets is described. In this algorithm, nets are classified based on the type of signal they carry. A table stores classification-dependent information including data to calculate minimum net-to-net spacing, sensitivity to parasitic capacitances, and the single-layer-only routing requirement. The routing channel is represented by a weighted directed graph. The graph represents relative positions of nets with the channel. The edge weights and directions in the graph are assigned to account for the analog routing concerns provided in the net classification table.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>