Analog Design Automation Research Articles

Qualitative data augmentation for performance prediction in VLSI circuits

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180 nm and 22 nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog circuits and digital cells. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

A Hybrid GA/ML-Based End-to-End Automated Methodology for Design Acceleration of Wireless Communications CMOS LNAs

A new methodology for the RF/mmWave analog design process, automation and acceleration, is presented in this work. The proposed framework was implemented so as to accelerate the design cycle of analog/RF circuits by creating a dataset in a fully automated manner and training a combination of machine learning models for the optimal design parameters’ prediction. machine learning polynomial regression was adopted to accelerate the design process, predicting the optimal design parameters’ values while genetic algorithm optimization was exploited for the dataset creation automation. To evaluate the efficiency of the proposed methodology, the framework was implemented for the design of a common source Low-Noise-Amplifier, using a 65 nm CMOS process node. The proposed methodology successfully tackles the design cycle speed-up, automation, and acceleration, utilizing machine learning prediction for the design parameters and genetic algorithm for the dataset creation automation instead of the classical, simulation-based, standard design methodology. The provided experimental results have shown the effectiveness of the proposed hybrid approach, creating very precise RF matching networks for LNA designs and achieving >99.9% wave transmission efficiency while reaching >99% accuracy on the parameters’ prediction task.

Generating the Generator: A User-Driven and Template-Based Approach towards Analog Layout Automation

Various analog design automation attempts have addressed the shortcomings of the still largely manual and, thus, inefficient and risky analog design approach. These methods can roughly be divided into synthesis and procedural generation. An important key aspect has, however, rarely been considered: usability. While synthesis requires sophisticated constraints, procedural generators require expert programmers. Both prevent users from adopting the respective method. Thus, we propose a new approach to automatically create procedural generators in a user-driven way. First, analog generators, which also create symbols and layouts, are utilized during schematic entry to encapsulate common analog building blocks. Second, automatic code creation builds a hierarchical generator for all views with the schematic as input. Third, the approach links the building block generators with the layout through an object-oriented template library that is accessible through generator parameters, allowing the user to control the arrangement. No programming is required to reach this state. We believe that our approach will significantly ease the transition of analog designers to procedural generation. At the same time, the templates allow for a “bridge” to open frameworks and synthesis approaches so that the methodologies can be both better spread and combined. This way, comprehensive frameworks of both synthesis-based and procedural-based analog automation methods can be built in a user-driven way, and designers are enabled to gain early layout insight and ease IP reusability.

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

Exploring the Advantages of Single-Ended-Input CMOS Self-Biased Amplifiers

This brief presents the analysis of self-biased topologies to implement single-ended-input CMOS amplifiers. We depart from basic amplifying stages to construct the self-biased circuits. We propose an amplifier based on the common-source and cascode configurations with active load, in which all three transistors are self-biased. This translates into important advantages for the amplifier: less power consumption since biasing circuits are no needed, and a robust design because all transistors are guaranteed to be in the saturation region even with process, temperature, or supply variations. The only drawback of this topology is the low power-supply rejection. A prototype was designed in a 130-nm CMOS technology to have a gain of 40 dB in the frequency band between 100 kHz and 5 MHz. The measurements of the circuit demonstrated that the amplifier fulfilled the specifications at the nominal voltage (1.2 V) while consuming 13 $\mu \text{A}$ . Furthermore, the circuit functions as amplifier for supply voltages as low as 400 mV and such high as 1.5 V, probing the flexibility of self-biased circuits. That flexibility can be explored in the future to design adaptive systems and to facilitate analog design automation.

Multi-objective optimization and visualization for analog design automation

The automated design of analog and mixed-signal circuits is a well-known subject of increasing technical and economical significance, e.g., sensory circuits for internet of things, cyber-physical systems, and Industry 4.0.The demand for rapid solution achievement under constraints, as, e.g., robustness, in established and emerging technologies as well as the migration between technologies gives incentive to automation activities. Existing approaches and tools still show improvement potential with regard to multi-variate modeling, efficient and multi-objective optimization, as well as transparence and user interaction options during the design. This paper presents new approaches applied within an emerging design environment, denoted as ABSYNTH, with an evolving self-learning architecture for efficient hierarchical optimization in a cascade, which includes function approximators and simulators trained by proven evolutionary optimization algorithms, as well as a novel domain-specific visualization of the optimization space and the trajectory of the design process. Nominal schematic-level sizing of the commonly used Miller, buffer, and folded-cascode amplifier circuits has been studied with our approach. For Miller, buffer, and folded-cascode, a cascade of harmony search and particle swarm optimization on SVR, ngspice, and cadence simulators was found to be roughly 4 times, 2.5 times, and 2.5 times faster, respectively, than the flat approach with equal or better results. In future work, we will improve the approach by including more demanding circuits, statistical deviations, circuit breeding, advanced optimization, and layout generation.

Towards Analog Design Automation using Evolutionary Algorithm: A Review

Analog circuits are the most important parts in many Integrated Circuit (IC) design. This paper reviews the basic concepts in analog design automation using evolutionary algorithm. Analog design problem is a multi objective problem; this can be solved by Evolutionary computation methods. Computation methods provide the set of feasible solutions for the optimal circuit design of analog integrated circuits. It is necessary to integrate both analog and digital in a single chip for real world communication. Due to system level integration we need analog design automation tool for IC design. This paper summarized recent start of art in analog optimization and also lists the survey of main people working in this field. Finally, we listed several open research problem to improve the analog design automation for analog IC using evolutionary computation.

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180nm and 40nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.

(Invited) The Human Factor in Mixed-Signal Design and Its Consequences for Design and Automation

The semiconductor industry historically has made strong statements about analog circuits to diminish in applications. In parallel electronic design automation (EDA) industry has been committed to enable a high level of analog design automation. However, today analog circuit design reality does not look very different to the status 10 years ago – and analog design is still a common discipline in semiconductor manufacturing. This paper will analyze reason why analog design is still important and why analog design automation is not as successful as its digital counterpart. It is shown that analog circuit complexity strongly increases with the trend towards building systems on chip. Therefore solving today’s mixed signal design problems is becoming urgent. Overall here the situation is not very different from the digital verification crisis we have seen some years back in the past.

Nullor Equivalents of Active Devices for Symbolic Circuit Analysis

The new pathological elements, the voltage mirror (VM) and current mirror (CM), have shown advantages in analog behavioral modeling and circuit synthesis. Recently, the floating mirror elements have been used to derive pathological sections to ideally represent various popular analog signal processing properties that involve differential or multiple single-ended signals. In order to take advantage of the symbolic nodal analysis (NA) of nullor-mirror networks, we present the nullor equivalents of a differential voltage cell, a differential voltage conveying cell, and a current replication cell in this paper. The proposed nullor equivalents can be used to represent many popular active devices in performing symbolic NA. Two representative filter circuits containing differential characteristics of active devices are given to verify the feasibility. We expect them to be used within an analog design automation environment to enhance circuit analysis and modeling.

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.

Electronic design automation using a unified optimization framework

This work proposes an object-oriented unified optimization framework (UOF) for general problem optimization. Based on biological inspired techniques, numerical deterministic methods, and C++ objective design, the UOF itself has significant potential to perform optimization operations on various problems. The UOF provides basic interfaces to define a general problem and generic solver, enabling these two different research fields to be bridged. The components of the UOF can be separated into problem and solver components. These two parts work independently allowing high-level code to be reused, and rapidly adapted to new problems and solvers. The UOF is customized to deal with several optimization problems. The first experiment involves a well-known discrete combinational problem, wihle the second one studies the robustness for the reverse modeling problem, which is in high demanded by device manufacturing companies. Additionally, experiments are undertaken to determine the capability of the proposed methods in both analog and digital circuit design automation. The final experiment designs antenna for rapidly growing wireless communication. Most experiments are categorized as simulation-based optimization tasks in the microelectronics industry. The results confirm that UOF has excellent flexibility and extensibility to solve these problems successfully. The developed open-source project is publicly available.

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Automated techniques for device sizing, for layout, and for basic statistical centering have been successfully deployed. However, successful component-level tools do not scale trivially to system-level applications. While a typical analog circuit may require only 100 devices, a typical system such as a phase-locked loop, data converter, or RF front-end might assemble a few hundred such circuits, and comprise 10 000 devices or more. And unlike purely digital systems, mixed-signal designs typically need to optimize dozens of competing continuous-valued performance specifications, which depend on the circuit designer's abilities to successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems. For purposes of synthesis or verification, these designs are not tractable when considered "flat." These designs must be approached with hierarchical tools that deal with the system's intrinsic design hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows

SIASCA: Interactive System for the Symbolic Analysis of Analog Circuits

To improve analog design automation (ADA) of electronic circuits, an interactive system for symbolic analysis called SIASCA is introduced. SIASCA includes schematic capture of a more general class of analog circuits, namely: operational transconductance amplifiers and current conveyors. The options of analysis are focused on calculating simplified symbolic expressions (SEs), representing the dominant behavior of a circuit, for AC and noise analysis. To minimize complexity in manipulating SEs, all active devices are modeled at different levels of abstraction by using nullors. Several examples demonstrate the suitability and usefulness of SIASCA to be used within ADA environments.

A C-T filter compiler - from specifications to layout

This paper presents an analog Design Automation tool implemented within the Cadence Edge system, using the Cadence programming language Skill and other useful Cadence tools. Given standard filter specifications, the tool generates Continuous-Time filter blocks implementing the desired function. A numerical optimization technique is used to cancel response errors, introduced by the non-ideal circuit elements available for real filter realizations. Except for an operational amplifier which must be provided by the user, component layout is performed by dedicated module generators, and the final filter layout is assembled using the Cadence Edge place & route program. In the current version of the program, the only available filter topology is the MOSFET-C topology. However, an hierarchical, object oriented approach is adopted, in order to ensure reusability and extensibility of the tool. Each general aspect of a filter design is accessed through a uniform interface from the higher level of hierarchy, allowing dedicated procedures depending on the particular implementation to deal with the details, without affecting the workings of the tool at the higher level of hierarchy.

Towards an analog system design environment

An analog circuit design environment and its key features are presented. These are multifunctionality, advanced modeling, novel simulation approaches, general sizing algorithms, hierarchy, and automatic and interactive layout generation capabilities. Also, several developments in the field of analog design automation are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>