AMBA AHB Research Articles

AMBA AHB Bus with Multiple Masters Using VHDL

This article depicts execution of DDR3 controller of AMBA Bus with four experts is portrayed in this paper. DDR3 controller is associated with the AMBA AHB Bus. It empowers development of squares of information from fringe to memory, memory to fringe, memory to memory, and fringe to fringe. This development of information lessens the heap on the processor. A DDR3 controller saves power in a framework by placing the CPU in a low force state. An AXI 4.0 execution in SOC configuration lessens the limits of correspondence by decreasing information rates. Proposed configuration utilizes AXI 4.0 conventions with memory regulator interface. AXI 4.0 convention upholds various IDs and channel handshaking rather than judge. In AXI 4.0, five individual exchange channels is proposed to convey in different expert and various slave frameworks so numerous bosses can discuss all the while with numerous slaves and wonderful parallelism is accomplished. All the control circuitry is synthesized using Xilinx 13.1 and simulation waveforms are achieved by using Modelsim 6.5e.

Verification of AMBA AHB Protocol using UVM

The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced verification testbench incorporates the illustrations regarding simulation result are analysed to evaluate the effectiveness of the proposed testbench and functional coverage is to check functionality of the design. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.

A Review on AMBA AHB Lite Protocol and Verification using UVM Methodology

A Review on AMBA AHB Lite Protocol and Verification using UVM Methodology

Viable System Verilog Assertions(SVA) Praxis in AMBA AHB-Lite Protocol Design

Digital integrated circuit(ic design entanglement has been far reaching since the demonstration by kil by in 1958.in this day and age system on chip(soc) design verification accommodate billion , more specifically trillion transistors designs came into existence due to artificial intelligence(ai) designs. The expertise designers tried to ramp up design process by using effective eda tools , still the time wheel move in recursive process. In order to accelerate time wheel of design process specified design methodology needed for every design. The overview of various design methodologies followed in the market now a days. Emulation performance by using veloce platform in bfm mode on ahb lite transmissions. Simulation by using software eda tools is slow going on wheel of design when we go for higher abstraction. Accelerated simulation and emulation using hardware is costly in contrast with software simulation. Prototyping is expedient. Formal verification and intelligent software simulations are frail. The possibility of selection between various hardware engines become ravelled. It develop into perspicuous only amalgamation of engines will assist design verification teams to be triumphant. In this design combination of hardware accelerated simulator as a combination of emulator used to accelerate time wheel by using arm amba ahb lite protocol as a design.

Design and Verification of AMBA AHB Lite Customized Slave Memory using Vivado

Design and Verification of AMBA AHB Lite Customized Slave Memory using Vivado

SystemVerilog based AMBA AHB Protocol

SystemVerilog based AMBA AHB Protocol

AMBA AHB Design: A Review

AMBA AHB Design: A Review

A multi-paradigm language for reactive synthesis

This paper proposes a language for describing reactive synthesis problems that integrates imperative and declarative elements. The semantics is defined in terms of two-player turn-based infinite games with full information. Currently, synthesis tools accept linear temporal logic (LTL) as input, but this description is less structured and does not facilitate the expression of sequential constraints. This motivates the use of a structured programming language to specify synthesis problems. Transition systems and guarded commands serve as imperative constructs, expressed in a syntax based on that of the modeling language Promela. The syntax allows defining which player controls data and control flow, and separating a program into assumptions and guarantees. These notions are necessary for input to game solvers. The integration of imperative and declarative paradigms allows using the paradigm that is most appropriate for expressing each requirement. The declarative part is expressed in the LTL fragment of generalized reactivity(1), which admits efficient synthesis algorithms, extended with past LTL. The implementation translates Promela to input for the Slugs synthesizer and is written in Python. The AMBA AHB bus case study is revisited and synthesized efficiently, identifying the need to reorder binary decision diagrams during strategy construction, in order to prevent the exponential blowup observed in previous work.

Parameterized Synthesis Case Study: AMBA AHB

We revisit the AMBA AHB case study that has been used as a benchmark for several reactive synthesis tools. Synthesizing AMBA AHB implementations that can serve a large number of masters is still a difficult problem. We demonstrate how to use parameterized synthesis in token rings to obtain an implementation for a component that serves a single master, and can be arranged in a ring of arbitrarily many components. We describe new tricks - property decompositional synthesis, and direct encoding of simple GR(1) - that together with previously described optimizations allowed us to synthesize a component model with 14 states in about 1 hour.

AMBA AHB 기반 SDRAM 컨트롤러 설계

In this paper, we introduce a SDRAM controller implemented on FPGA. Modern embedded system adopts SDRAM as a memory to meet the high capacity memory demands. Our SDRAM controller is written in Verilog and verified on an FPGA, demonstrating the functionality along with ARM Cortex-M0, supporting AMBA AHB.

Asynchronous FIFO Design with Gray code Pointer for High Speed AMBA AHB Compliant Memory controller

An improved technique for FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains and asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. This method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic. This FIFO design is used to implement the AMBA AHB Compliant Memory Controller. Which means, Advanced Microcontroller Bus Architecture compliant Microcontroller .The MC is designed for system memory control with the main memory consisting of SRAM and ROM.

Synthesis of AMBA AHB from formal specification: a case study

The standard hardware design flow involves: (a) design of an integrated circuit using a hardware description language, (b) extensive functional and formal verification, and (c) logical synthesis. However, the above-mentioned processes consume significant effort and time. An alternative approach is to use a formal specification language as a high-level hardware description language and synthesize hardware from formal specifications. Our work is a case study of the synthesis of the widely and industrially used AMBA AHB protocol from formal specifications. Bloem et al. presented the first formal specifications for the AMBA AHB Arbiter and synthesized the AHB Arbiter circuit. However, in the first formal specification some important assumptions were missing. Our contributions are as follows: (a) We present detailed formal specifications for the AHB Arbiter incorporating the missing details, and obtain significant improvements in the synthesis results (both with respect to the number of gates in the synthesized circuit and with respect to the time taken to synthesize the circuit), and (b) we present formal specifications to generate compact circuits for the remaining two main components of AMBA AHB, namely, AHB Master and AHB Slave. Thus with systematic description we are able to automatically and completely synthesize an important and widely used industrial protocol.

Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis

A new machine learning SoC (MLSoC) for multimedia content analysis is implemented with 16-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area in 90-nm CMOS technology. Different from traditional VLSI architectures, it focuses on the coacceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve tera-scale performance. In the dual stream processor (DSP) architecture, the data are transferred between processors and the high-bandwidth dual memory (HBDM) through the local media bus without consuming the AMBA AHB bandwidth. The image stream processor (ISP) of the MLSoC can handle common window-based operations for image processing, and the feature stream processor (FSP) can deal with machine learning algorithms with different dimensions. The power efficiency of the proposed MLSoC is 1.7 TOPS/W, and the area efficiency is 81.3 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Network interface design based on mutual interface definition

This paper proposes a novel network interface design method, referred to as mutual interface definition based method. It decouples resource dependent part (RDP) from resource independent part (RIP) by mutual interface definition. These two parts can be designed independently, thus the design flexibility and reusability of network interface can be enhanced. Moreover, a network interface component library consisting of multiple RDP and RIP components is proposed to be built. The networks-on-chip designers can choose appropriate components from the library to construct network interface design. From the perspective of RDP, the network interface achieves backward compatibility with the existing protocols such as AMBA AHB and OCP. From the perspective of RIP, the network interface provides a configurable structure supporting multicast transfer and adaptive routing algorithm extensions. The proposed network interface designs are implemented in TSMC 90-nm CMOS standard cell technology and can work at the frequency of 1.12 GHz to 1.35 GHz.

HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms

Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.

Provably correct on-chip communication

Hardware module reuse is a standard solution to the problems of increasing complexity of chip architectures and pressure to reduce time to market. In the absence of a single module interface standard, predesigned modules for “plug-and-play” usually require a converter between incompatible interface protocols. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the HDL implementation level or grossly simplify the structure of the protocols considered. This work presents a state-machine-based formalism for modeling bus-based communication protocols and a notion of protocol compatibility and of correct conversion between incompatible protocols. This formalism is used to derive algorithms for checking protocol compatibility and for provably correct, automatic converter synthesis. Experiments with automatic converter synthesis between different configurations of widely used commercial bus protocols, such as AMBA AHB, ASB APB, and the Open Core Protocol (OCP) are discussed. The work here is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modeling of protocol characteristics that is also close to HDL.

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.The techniques underlying Flexbus are general, and are applicable to a variety of bus standards. We have implemented Flexbus as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied Flexbus to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UMTS turbo decoder. Our results show that Flexbus provides gains of up to 34.55 % in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.

Graph based test case generation for TLM functional verification

Describing complex systems at a high level of abstraction provides designers with the possibility of exploring multiple SoC design architectures before committing to the low level-details of a complete implementation. Transaction level modeling understandably expedites the design simulation and verification. During the verification process, generating good test cases plays a significant role in determining the quality of the design. Inadequate test cases may cause bugs to remain. In this paper, first, in order to generate test cases for a TL model, we present a Control-Transaction Graph (CTG) which describes the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and transactions represent the interactions such as synchronization between modules. Second, we define dependent paths ( DePaths) on the CTG as test cases for a transaction level model, which can find communication errors in simulation. We also give coverage metrics for a TL model to measure the quality of the generated test cases. Finally, we apply our method on the SystemC model of AMBA–AHB bus and JPEG encoder and generate test cases based on the CTG of these models.

Specify, Compile, Run: Hardware from PSL

We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs that are correct by construction. The idea of automatic synthesis from specifications is old, but used to be completely impractical. Recently, great strides towards efficient synthesis from specifications have been made. In this paper we extend these recent methods to generate compact circuits and we show their practicality by synthesizing a generalized buffer and an arbiter for ARM's AMBA AHB bus from specifications given in PSL. These are the first industrial examples that have been synthesized automatically from their specifications.

A functional formalization of on chip communications

Abstract This paper presents a formal model and a systematic approach to the validation of communication architectures at a high level of abstraction. This model is described mathematically by a function, named GeNoC . The correctness of GeNoC is expressed as a theorem, which states that messages emitted on the architecture reach their expected destination without any modification of their content. The model identifies the key constituents common to all on chip communication architectures, and their essential properties from which the correctness theorem is deduced. Each constituent is represented by a function that has no explicit definition but is constrained to satisfy the essential properties. Thus, the validation of a particular architecture is reduced to the proof that its concrete definition satisfies the essential properties. In practice, the model has been defined in the logic of the ACL2 theorem proving system. We illustrate our approach on several architectures that constitute concrete instances of the generic GeNoC model. Some of these applications come from industrial designs, such as the AMBA AHB bus or the Octagon network from ST Microelectronics.