Alternative Bit Research Articles

Trialling Locally Made, Low-Cost Bits to Improve Bit-Related Welfare Problems in Cart Horses: Findings from a Study in Senegal

Bits used for cart horses in Senegal are typically made of recovered construction iron and often have defects related to design, shape, fit and metal quality. Consequently, there is widespread presence of bit-related oral injury amongst these equids. It was hypothesised that improving bit design would ameliorate bit-related welfare issues for working cart horses. This study aimed to develop locally made alternative bit prototypes and test their efficacy as less harmful to working horses, and their acceptability to their drivers. Eight animal-based welfare indicators (four physical and four behavioural) were designed to measure positive or negative effects of the new bits. Following a testing phase to appraise and mitigate potential animal welfare risk associated with the alternative bit designs, a total of 540 driver/horse combinations were opportunistically selected across five municipalities in Senegal. Welfare indicators were observed when new bits were introduced and again after 21 weeks of daily use. The results indicated statistically significant improvements in all welfare indicators measured (i.e., lesions on lip commissures, tongue, buccal mucosa and bars; and open mouth, tongue loll, head toss/shake, and head tilt/turn behaviours). None of the drivers reported any difficulty with horse control, nor chose to revert back to their original bits. Whilst acknowledging the limitation of inability to control all potential confounding variables, these preliminary findings suggest the bit itself as an important contributor to oral injury, and the possibility to improve this through alternative bit design that is low-cost, locally produced and acceptable to drivers.

Dual pillar spin-transfer torque MRAMs for low power applications

Electron-spin based data storage for on-chip memories has the potential for ultra-high density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we discuss the design challenges associated with spin-transfer torque (STT) MRAM in its state-of-the-art configuration. We propose an alternative bit cell configuration and three new genres of magnetic tunnel junction (MTJ) structures to improve STT-MRAM bit cell stabilities, write endurance, and reduce write energy consumption. The proposed multi-port, multi-pillar MTJ structures offer the unique possibility of electrical and spatial isolation of memory read and write. In order to realize ultralow power under process variations, we propose device, bit-cell and architecture level design techniques. Such design alternatives at multiple levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

The need for power-efficient memories that are capable of operating at low supply voltages has led to the development of several alternative bit cell topologies. The majority of the proposed designs are based on the 6T bit cell with the addition of devices and/or peripheral techniques aimed at reducing leakage and enabling read and write functionality at lower operating voltages. In this brief, we propose a reduced transistor count bit cell that is fully functional in the sub-threshold (ST) region of operation. This asymmetric 5T bit cell is operated through a single-ended read and differential write scheme, with an option for operation as a two-port cell with single-ended write. The bit cell's operating scheme provides a non intrusive read operation and improved write margins for robust functionality. In addition, the circuit's asymmetric characteristic provides a low-leakage state with an additional 5X static power improvement over the reduction inherently achieved through voltage lowering. The proposed bit cell was designed and simulated in a 40-nm commercial CMOS process and is shown to be fully operational at ST voltages as low as 400 mV under global and local process variations. At this supply voltage, a 21X static power reduction is achieved, as compared to the industry-standard 6T bit cell, operated at its minimum supply voltage.

POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters

While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversion and for the remaining processing to be performed in standard multi-bit binary at the Nyquist rate and with a resolution mandated by the dynamic range and noise. Using a Finite Impulse Response filter design as an example, we compare the area and performance of this conventional approach with the alternative single bit approach that operates directly on the ΣΔ data stream using ternary coefficients {?1, 0, +1} derived from the ΣΔ modulation of the target impulse response. Filters exhibiting approximately equivalent spectral performance in the two alternative approaches were developed using VHDL and simulated using some commercial FPGA types. In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates. They also exhibit up to 40% higher performance and offer useful area savings at lower filter orders. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. The simplicity and low power of the ΣΔ approach makes it applicable to mobile communication processing using low cost FPGA technology.

Applications of Finite Linear Temporal Logic to Piecewise Linear Aggregates

In this paper, we consider piecewise linear aggregates (PLA) and a possibility to use a linear temporal logic for analysis of their performance over finite structures (finite linear temporal logic (LTL)). We describe a calculus where the search is performed with respect to a context of the formula. An important aspect of finite LTL is the simplicity of its model of time and actions. PLA is used for description of numerous complex systems. The answers about the behavior of the aggregate are got by finding an interpretation in which all the formulas describing the work of the aggregate are true. This is illustrated by formalizing alternative bit protocol (ABP) task. We describe the ABP by putting it in the form of a planning problem. From the obtained model, we can find a finite sequence of actions to be executed in order to achieve the goal. In addition, an alternative bit protocol problem is described using the planning domain description language (PDDL). We report the results of experiments conducted using the LPG-TD planner.

CCK modulation: beyond Wi-Fi

The full-rate IEEE 802.11b standard for wireless local area networks, also known as Wi-Fi, employs 256-ary complementary code keying (CCK). For applications that do not require adherence to the standard, it may be desirable to use forward error correction coding with CCK, but the bit-to-symbol mappings used in IEEE 802.11b degrade the performance of most standard binary codes. We show that a standard binary convolutional code performs much better with alternative bit mappings, and we demonstrate that chip scrambling gives additional improvement.

Bit and symbol error rates for complementary code key modulation with alternative bit mappings

Full-rate modulation in the IEEE 802.11b standard employs complementary code keying (CCK) with a set of 256 signals that provides 11 Mb/s in favorable indoor propagation environments. The bit-to-symbol mapping of IEEE 802.11b is suboptimal for applications in which the bit error probability is important. We present analytical and simulation results on the bit and symbol error probabilities for IEEE 802.11b CCK and alternative bit mappings that improve CCK systems that need not adhere to the standard.

Asynchronous decision making in a memorized paddle pressing task

This paper presents a method for asynchronous decision making using recorded neural data in a binary decision task. This is a demonstration of a technique for developing motor cortical neural prosthetics that do not rely on external cued timing information. The system presented in this paper uses support vector machines and leaky integrate-and-fire elements to predict directional paddle presses. In addition to the traditional metrics of accuracy, asynchronous systems must also optimize the time needed to make a decision. The system presented is able to predict paddle presses with a median accuracy of 88% and all decisions are made before the time of the actual paddle press. An alternative bit rate measure of performance is defined to show that the system proposed here is able to perform the task with the same efficiency as the rats.