Thermal issue has significant effect on the reliability and performance of integrated circuits with the increase of integrated density, especially for 2.5-D and 3-D heterogeneous integration packaging systems. In this paper, a new highly efficient 3-D transient thermal distribution model has been constructed to capture the heat conduction behavior of multiple heat sources for chiplet heterogeneous integration (CHI) by improving the alternating direction implicit finite difference method (ADI-FDM). Firstly, a new floating optimization algorithm (FOA) of coefficient matrix assignment of heat conduction equation and a new boundary treatment utilizing virtual points are proposed to modify the ADI-FDM and improve the model efficiency of thermal analysis. Furthermore, a universal equivalent thermal conductivity model is also built up to describe the design features of through silicon via (TSV), bump and redistribution layer structures, which can enhance the flexibility of FDM-based thermal simulator. Compared with previous finite element analysis results, the present FOA-accelerated thermal model can not only obtain an accurate simulation result of temperature profile, but also give a simulation efficiency of 3.74 times faster than Douglas-Gunn approach for the coefficient matrix assignment. Finally, the effect of power consumption variation and the floorplaning effects of chiplets, TSVs and bumps on the temperature distribution are investigated in detail by utilizing the present FOA-based thermal solver. The simulated results of the present work demonstrate the viability and computational efficiency for temperature field optimization and indicate that the new proposed simulator is helpful in thermal analysis of packaging structures and can be adopted to assist in physical design optimization of 2.5-D CHI or 3-D heterogeneous stacked chips.
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