Alternative Phase Opposition Disposition Research Articles

Design and implementation of single DC-link based three-phase multilevel inverter with CB-PWM techniques

Simulation and implementation of a single DC-link-based three-phase inverter are investigated in this article. The primary focus is on designing a single DC-link three-phase inverter for high power applications. Unlike conventional inverters that require 600 V to generate 400 V (RMS) at the output, the proposed system achieves this with only 330 V, facilitated by a 12-terminal 1:1 transformer. The system employs Proportional Integral (PI) and Neural Network (NN) controllers to optimize performance. Various Carrier-Based Pulse Width Modulation (CB-PWM) techniques, including Phase Disposition (PD), Phase Opposition Disposition (POD), and Alternative Phase Opposition Disposition (APOD), are implemented and evaluated based on Total Harmonics Distortion (THD) concerning the Modulation Index (MI) of the inverter. The proposed inverter achieves a THD reduction to 4.8%, demonstrating superior performance compared to recent studies. The system’s performance is validated through extensive MATLAB/Simulink simulations and practical implementation using XILINX FPGA software, confirming the efficacy of the proposed design.

Design DC/AC Converter for Renewable Energy Sources

Multilevel inverters are vastly used in power systems and “renewable energy sources” (RES) to provide an AC voltage with a low level of harmonic contents. This paper aims to design a 9-level inverter for RES such as photovoltaic (PV), wind turbines, and fuel cells… etc. The proposed inverter is constructed by 12 IGBT switching devices where all of which are powered by 4 DC sources of 81 V without balancing capacitors to make DC voltage 324 V. A Phase disposition (PD), alternative phase opposition disposition (APOD), and POD with a slight phase shift are the methods of modulations that are used to provide a sinusoidal waveform of the output voltage and current. The minimum “Total harmonic distortion” (THD %) of the output voltage of the inverter is 13.68 % and 1.7 % in the cases where there is no filter and with filter conditions respectively. The load voltage is regulated by a PI controller based on the RMS value of the inverter output voltage.

Multilevel inverter: harmonic analysis with and without filters for RL load using SPWM techniques

Multilevel inverter (MLI) gains more attraction compared to conventional inverter as it generates a staircase output voltage that mimics sine waves of desired output voltage. Cascaded H-bridge (CHB) topology is taken into consideration owing to several benefits over conventional inverters. Various levels of CHB (3 and 5 level) inverters are compared on diverse parameters. In this paper level shift sinusoidal pulse width modulation technique is considered resulting in reduced lower order harmonic (LOH) distortion and improve the quality of output current and voltage depending on the load. Since, the LOH are too dangerous for power electronic circuits. An attempt to shift all the LOH above 50th order depending on the modulation technique with analogy for selecting an appropriate switching frequency is highlighted. The effect of change in switching frequency and modulation index (MI) on RMS output voltage, % voltage total harmonic distortion (VTHD), output power factor with different modulation techniques such as phase disposition pulse width modulation (PsD PWM), phase opposite disposition (POD PWM), alternative phase opposition disposition (APOD PWM) is portrayed in the paper. Further, to boost the performance a unique filter circuits with optimal design values of Inductance and capacitance driven with IEEE 519-2022 standards. The effectiveness in terms of with and without filter is verified and validated using MATLAB.

Phase Shift APOD and POD Control Technique in Multi-Level Inverters to Mitigate Total Harmonic Distortion

Multi-level inverters are widely employed to generate new energy because of their huge capacity and benefits in sound control performance. One of the critical areas of study for multi-level inverters is control strategy research. In this study, the control strategy for a multi-level inverter—which is frequently employed in HVDC and FACTS systems—is designed. An asymmetrical D.C. voltage source is supplied to create the appropriate output voltage waveform with fewer total harmonic distortions (THDs) at the output voltage and current waveforms. In this work, the pulse width modulation techniques of POD (phase opposition disposition) and APOD (alternative phase opposition disposition) MC PWM are applied to a multi-level inverter to generate the seven-level output voltage waveform. This study presents an enhanced variable carrier frequency APOD control approach that can successfully lower the overall harmonic distortion rate. The design and completion of the phase-shifting POD and APOD control strategies are followed by an analysis and comparison of the THD situation under various switching frequencies and a simulation and verification of the control strategy using MATLAB simulation. The TI DSP-based control approach has been programmed. The APOD technique increases the output voltage’s THD to 18.27%, while the output current waveform’s THD is reduced to 15.67% by utilizing the APOD PWM technique. Using the POD PWM approach increases the total harmonic distortion (THD) of the voltage waveform by 18.06% and the output current waveform’s THD by 15.45%.

Investigation of PWM methods for a 9 level boost inverter using CD-type carriers

The article suggests a new boost inverter topology that uses two switching capacitors and a single dc source to produce an output voltage waveform with nine levels. There are no sensors or other electronics required because the capacitor voltages balance themselves. An input dc boost converter is not necessary when using an inverter because its output voltage is frequently two times greater than its input voltage, especially when the inverter is powered by a natural source. The new modulation techniques that have been proposed for CD-type carrier waves have better efficiency, higher RMS voltage, and less harmonic distortion (THD).The efficacy of the suggested carriers has been confirmed by phase disposition (PD), alternate phase opposition disposition (APOD), and phase opposition disposition (POD) investigations. The effectiveness of each technique described under 9LBI has been evaluated using a MATLAB/Simulink configuration. The operation and dynamic performance of the suggested architecture have been modelled using MATLAB/ SIMULINK.

A Fifteen-Level Reduced Switch Count Multilevel Inverter with Multicarrier PWM

A multilevel inverter performs a major role in increasing the range of the level of output voltage without the use of a transformer in the power sector. Here an asymmetrical 15-level multilevel inverter fed from three unequal voltage sources has been proposed. The various modes of the conduction of the eight switches with the switching pattern are discussed with the circuit’s operation. The performance of the circuit is analysed using various techniques under MC-PWM methodologies such as Phase disposition (PD) PWM, Alternate POD (APOD) PWM, and Phase Opposition Disposition (POD) PWM. Key Finding: The logical expression used for generating the pulse pattern of the above techniques using the level shifting PWM technique to reduce the harmonics is performed, simulated, and compared by implementing three techniques for linear and non-linear load. The performance in terms of THD of output voltage under various modulation indexes is compared for various Llvel-shifting techniques. The performance of this 15L-MLI is simulated using MATLAB/Simulink and implemented in a prototype hardware model.

Design and Performance Analysis of New Multilevel Inverter for PV System

Multilevel inverters (MLIs) have recently attracted more attention in medium-voltage and high-power applications as they can provide an effective interface with photovoltaic (PV) systems. Conventional MLIs are used to generate higher voltage levels, which improve power quality and reduce the requirement for passive filters. However, recent research has focused on designing new MLI topologies using reduced switch counts and less voltage stress. This study, as such, proposes a new nine-level symmetric MLI for PV systems with a minimum number of switches. This decrease in the number of switches reduces the voltage stress across the switches and the number of driving circuits, which lowers the complexity of the control circuit and, as a result, lowers the cost and size of the system. This article compares the proposed MLI with other topologies based on the DC sources, switches count, gate driver circuits (Ngd), total standing voltage per unit (TSVPU), cost function (CF), and components count per level (CC/L). The proposed topology is integrated with the PV system. MATLAB software is used to evaluate the performance of MLI at step change in irradiance and under variable load conditions. The total harmonic distortion (THD) of the proposed topology is reduced with the implementation of phase disposition pulse width modulation (PD-PWM). In addition, PD-PWM is compared with phase opposition disposition pulse width modulation (POD-PWM) and alternative phase opposition disposition pulse width (APOD-PWM) modulation techniques. The simulation results reveal the improved performance of the proposed topology at variable irradiance and under varying load conditions. The comparison results reveal minimum (TSVPU), CC/L, CF, and switch count compared to existing topologies. Hence, the proposed topology of MLI is cost-effective and superior in all aspects compared to other topologies. In summary, it offers overall improved performance, and thus, it is feasible for the PV system.

PI controller for photovoltaic-fed novel multilevel inverter topologies

This research describes the analysis and design of a unique 7-level and 9-level multi-level inverter topology with fewer DC power supplies and power switches, and a comparison using pulse width modulation (PWM). Comparisons of 7-level and 9-level multi-level inverters that analyze characteristics using optimal nearest level modulation (ONLM) technology are made using various PWM approaches such as nearest level modulation (NLM) technique, phase disposition (PD), phase opposition disposition (POD), and alternate phase opposition disposition (APOD). The output is evaluated based on a high Vrms, low total harmonic distortion (THD) harmonic profile. The controller is based on artificial intelligence (AI) and machine learning (ML) techniques. ONLM techniques are used to measure the voltage harmonics of the full load, several DC offset values are used. The control technology provided is validated using MATLAB/Simulink simulation tools and laboratory-based experimental testing.

Hardware Design and Implementation of FPGA Controlled Seven-Level Reduced Switch MLI

The paper proposes the design of a seven-level reduced switch multi-level inverter (7LRS-MLI) topology. The design produces a seven-level staircase output waveform with fewer components (seven power switches), thus reducing the cost and area and improving the performance of the design, i.e. increasing efficiency and reducing switching loss effectively. Both symmetric and asymmetric configurations have been implemented and the results are discussed in the paper. A comparison of the proposed structure with other recent seven-level structures has been illustrated. The simulation (using MATLAB/SIMULINK software) and experimental validation of 7LRS-MLI also have been performed for R, RL load, change in load and change in a modulation index (MI). Field programmable gate arrays (FPGA) have been used for digital implementation of the switching waveforms which reduces design time and improves flexibility. For switching devices, the alternative phase opposite disposition pulse width modulation (APOD-PWM) technique is used at 500 Hz and 5 kHz. The voltage and current total harmonic distortion (THD) profiles are also computed during the simulation and experimental validation.

A reconfigurable integrated level shifted carrier based PWM method for modular multilevel converters

This article presents a reconfigurable integrated level shifted carrier‐based pulse width modulation (ILSC‐PWM) method for modular multilevel converters (MMCs). The principles of basic level shifted carrier‐based PWM (LSC‐PWM) methods such as phase disposition PWM (PD‐PWM), phase opposition disposition PWM (POD‐PWM) and alternate phase opposition disposition PWM (APOD‐PWM) methods are combined to develop the concept of reconfigurable ILSC‐PWM method. The main objectives of the proposed reconfigurable ILSC‐PWM method is to develop the pulse width modulated output voltage with both half‐wave and quarter‐wave symmetries and to reduce the total harmonic distortion (THD). A simplified mathematical approach is developed to formulate reconfigurable single ILSC wave for MMC with N number of submodules (SMs) per arm. The functionality and performance of the reconfigurable ILSC‐PWM method are carried out on three‐phase five‐level MMC in MATLAB/Simulink. A hardware prototype of single‐phase five‐level MMC is designed for experimental validation. The proposed ILSC‐PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field programmable gate array (FPGA). Computer Simulations and laboratory experimental results are presented. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Level-Shift PWM Control of a Single-Phase Full H-Bridge Inverter for Grid Interconnection, Applied to Ocean Current Power Generation

A small prototype of a 5-level single-phase full H-bridge inverter for ocean current applications is presented. The inverter was designed applying level-shift control in pulse-width modulation (LS-PWM), and experimental tests were conducted using a variety of modulation subschemes, including in-phase disposition (IPD), alternate-phase opposition–disposition (APOD), and phase opposition–disposition (POD). The test results were examined for harmonic content and voltage total harmonic distortion (THDV). The results suggest that the inverter presents a viable solution with significant potential for the development of a larger three-phase inverter model that can be used to connect ocean current power sources to the electrical grid.

Capacitor-Voltage Self-Balance Seven-Level Inverter With Unequal Amplitude Carrier-Based APODPWM

In this article, a seven-level inverter based on bridge modular switched-capacitor circuits is presented. The inverter cannot only obtain dc-dc boosting conversion ability but also own capacitor voltage self-balance capability. Meanwhile, some of the switches can be operated under line voltage frequency, which makes the control strategy simpler and reduces the switching loss. More importantly, a new unequal amplitude carrier-based alternative phase opposition disposition pulsewidth modulation method is proposed to control the inverter, where the amplitude of the carrier wave will change based on the output voltage level. Under the proposed strategy, the inverter can output seven different voltage levels and the capacitor voltage self-balance can be realized during the switching period, the quality of the output waveforms can be improved remarkably. Last, a loss analysis within the two time-scale of switching period and 1/4 line voltage period is presented to give the loss insight. The simulation and experimental results verify the correctness and practicability of these analyses.

A hybrid level shifted carrier‐based PWM technique for modular multilevel converters

This paper presents a hybrid level shifted carrier-based pulse width modulation (HLSC-PWM) technique for modular multilevel converters (MMCs). The concept of the proposed HLSC-PWM method is developed by combining the principles of phase disposition PWM (PD-PWM), phase opposition disposition PWM (POD-PWM), and alternate phase opposition disposition PWM (APOD-PWM) methods. The main aim of the proposed HLSC-PWM method is to generate an output voltage with half-wave and quarter-wave symmetries. The generated symmetrical PWM output voltage based on the proposed HLSC-PWM method provides less total harmonic distortion (THD) and enhances the DC-Link voltage utilization (DCLVU). A generalized mathematical model is formulated to develop a single HLSC for MMC with an N number of submodules (SMs) per arm. Theoretical analysis of DCLVU for the proposed method is described. The functionality and performance of the HLSC-PWM method are carried out on a three-phase five-level MMC in MATLAB/Simulink. A hardware prototype of a single-phase five-level MMC is designed for experimental validation. The proposed HLSC-PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field-programmable gate array (FPGA), simulation and experimental results are presented.

Design and Development of N-Level Symmetrical Multilevel Inverter Topology with Reduced Switches

In this paper, 11-level multilevel inverter with reduced power switch configuration is developed and investigated. This proposed configuration can be extended for [Formula: see text] levels with the required number of power switches. Comparative analysis between the proposed multilevel inverter topology and well-known existing multilevel inverter topologies is carried out. Fundamental switching angle calculation for the power switches of the proposed topology has been optimized using black widow optimization algorithm technique and also the proposed topology has been tested with the classical multicarrier alternative phase opposition disposition PWM technique. To test the effectiveness of the proposed topology, different tests have been conducted such as testing with different modulation indexes, DC input voltages, load settings and voltage ride-through capabilities. This paper presents various simulation and experimental results under various operating conditions to prove the performance of the proposed multilevel inverter topology.

Analysis on three phase cascaded H-bridge multilevel inverter based on sinusoidal and third harmonic injected pulse width modulation via level shifted and phase shifted modulation technique

This work proposes a comparative analysis of sinusoidal and third harmonic injected reference signal modulation accompany with level-shifted PWM technique named as phase disposition (LSPD), phase opposition disposition (LSPOD), and alternate phase opposition disposition (LSAPOD) and phase-shifted PWM technique. Switching pulses from both reference signal and PWM technique have been fed into three phase eleven level cascaded H-bridge multilevel inverter (CHBMLI) fed on a resistive-inductive load with the modulation depth (MD) set to varied from 80% to 100%. For voltage source inverter, total harmonic distortion (THD) content is critical and must be within the allowable range. To prove the feasibility of the reference signal with carrier signal schemes, the entire simulation of the modulation techniques is established and conducted via the Simulink environment. According to the analyzed result, the performance is acceptable in terms of %THDV and %THDI values. Simulation analysis also indicates, at full modulation depth, due to higher fundamental output voltage component produces via the THIPWM modulation technique compared to the SPWM technique, this causes higher %THDV value.

A Voltage Balancing Scheme for Modular Multilevel Converter Based on Charge Variation in Each Cycle

This article presents a voltage balancing scheme for a modular multilevel converter (MMC) based on capacitor charge variation in each fundamental cycle. An in-depth theoretical analysis of stored charge variation for the concept is described. A new hybrid pulsewidth modulation (PWM) sequence is proposed based on a rotation strategy to achieve capacitor voltage balancing without sensing the capacitor voltages or arm currents. The rotation strategy provides the freedom of finding the best possible sequence to achieve capacitor voltage balancing. This reduces hardware, software burden and overall cost of the design implementation. The functionality and performance of the balancing strategy with new hybrid PWM sequence are carried out over wide range of modulation index (M) for three-phase five-level MMC in MATLAB/Simulink. A hardware prototype of single-phase five-level MMC is designed for experimental validation. The proposed hybrid PWM sequence is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field-programmable gate array using alternate phase opposition disposition PWM method. Simulation and experimental results are presented.

M-Type and CD-Type Carrier Based PWM Methods and Bat Algorithm-Based SHE and SHM for Compact Nine-Level Switched Capacitor Inverter

This paper presents new and efficient modulation techniques applied on the recently introduced compact nine-level switched-capacitor inverter (C9LSCI). The paper also discusses the performance of the inverter under selective harmonic elimination (SHE) and mitigation (SHM) based on the heuristic Bat-Algorithm (BA) technique. Two new modulation techniques employing CD-type carrier waves and M-type carrier waves are proposed, showing a rise in efficiency, an increase in RMS voltage, reduction in capacitor voltage ripple, and a reduction in harmonic distortion (THD). Four recently introduced modulating signals, namely the third harmonic injection, thirty-degree bus clamped PWM (THTDBCPWM), third harmonic injection sixty-degree bus clamped PWM (THSDBCPWM), one pole clamped PWM (OPCPWM). Loss balancing two-pole clamped PWM (LBTPCPWM) are applied to the inverter with the proposed carriers, and a comparative analysis is carried out on different performance parameters. The proposed carriers' efficacy in Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD), and Phase Disposition (PD) is validated. Further, Bat algorithm (BA) is applied as a heuristic approach to determine the optimum angles for the application of SHE and SHM. The efficacy of all the above techniques on the C9LSCI is verified in MATLAB/Simulink environment and further validated on an experimental setup.

Performance Evaluation of Cascaded and Reduced Switch Multilevel Inverter Using Modified Carrier Based PWM Technique

This paper proposes an improved harmonic distorted modified triangular carrier-based multicarrier pulse width modulation for generating the switching pulses of a multilevel inverter. This modified triangular wave consists of a triangular wave bearing a close resemblance to an ‘M’ shaped wave. The design of this carrier signal has been optimized to maintain a low level of total harmonic distortion (THD), while increasing the fundamental o/p voltage to ensure the effective DC voltage utilization. Moreover, this optimization reduces the switching losses and improve the efficiency of the power inverter. With the help of this carrier signal, High-frequency alternative phase opposition disposition pulse width modulation (APODPWM) is generated. This new control scheme has been applied to seven levels of conventional cascaded H-bridge with reduced switch multilevel inverter. The output is compared with conventional carrier-based APODPWM. The comparison is made in terms of THD, fundamental output voltages and inverter losses. To ensure quality performance, conventional carrier and modified carrier-based multicarrier PWM topologies are used for the Cascaded seven-level inverter with reduced switch seven-level inverter having a carrier frequency of 2 kHz and modulation index of 0.8-1.30. According to the simulation results, by using the proposed modulation scheme the THD and the switching loss were reduced by 9.64[%] and 4.2[%] respectively. Besides, the proposed modulation technique increases the fundamental output voltages. The total simulation process is done in MATLAB Simulink environment.
 GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 6(1), Dec 2019 P 12-19

Analysis of Cascaded Multilevel Inverter with a Reduced Number of Switches for Reduction of Total Harmonic Distortion

Multilevel inverters (MLI) are aligned with lower harmonics and less commutation losses, which offer high power capacity. MLI is one of the best widespread converters due to its ability to eliminate the harmonic distortion without dropping the converter power output. The cascaded MLI is utilized for a reduced number of switches. In this topology, the switching angles at fundamental frequency are attained by solving the selective harmonic eliminations using sine cosine algorithm. This attains the desired output voltage with the elimination of certain lower order harmonics. In this paper, the analysis of seven-level cascaded MLI is presented with the scheme of carrier-based modulation techniques i.e. Phase-Disposition (PD), Phase-Opposition Disposition (POD) and Alternative Phase-Opposition Disposition (APOD). The Artificial intelligence (AI) is carried out for PD technique. These techniques are capable of defining the required switching angles to eliminate the preferred values of harmonics. The harmonic contents of output voltage in carrier-based modulation are observed with the indices, such as the modulation index with frequency modulation index and amplitude modulation index. The simulation results are obtained for seven-level inverter using MATLAB/SIMULINK. The hardware implementation is carried out using Main Power Management IC TPS65217C Beagle Bone Black Board for seven-level open loop control to justify the achievement of the suggested topology.

A Novel 9-Level Switched Capacitor Inverter Using Different Carrier Based PWM Techniques

In this paper, a new 9-level inverter employing switched capacitor technique is proposed. Three bidirectional voltage blocking switches are employed to connect the four H-bridges and to incorporate the three switched capacitors. The proposed multilevel inverter (MLI) circuit outputs a 9-level waveform with a maximum boosting factor of four. Unlike the already established switched capacitor based MLI consisting of two stages the proposed MLI is single stage inverter. The switches in the proposed MLI is subjected to a low value of voltage stress equal to Vdc. The proposed MLI is further analyzed by using various multicarrier sinusoidal PWM technique such as Phase Shift PWM (PSPWM), Phase disposition PWM (PDPWM), Phase Opposition Disposition PWM (PODPWM), Alternate Phase Opposition Disposition PWM (APODPWM) and Variable Frequency PWM (VFPWM).