Altera Field Programmable Gate Array Research Articles

FPGA-Based Hardware-in-the-Loop (HIL) Emulation of Power Electronics Circuit Using Device-Level Behavioral Modeling

Accurate models of power electronic converters can greatly enhance the accuracy of hardware-in-the-loop (HIL) simulators. This can result in faster and more cost-effective design cycles in industrial applications. This paper presents a detailed hardware model of the IGBT and power diode at the device level suggested for emulating power electronic converters on a field programmable gate array (FPGA). The static visualization of the IGBT component involves an arrangement of equivalent models for both the MOSFET and bipolar transistor in a cascading configuration. The dynamic aspect is represented by inter-electrode nonlinear capacitances. In an effort to expedite the development process while still producing reliable results, the algorithm for the simulation system was built utilizing FPGA-based rapid prototyping via the HDL Coder in MATLAB software (R2019b). Essentially, the HDL Coder transforms the Simulink blocks of these devices within MATLAB into a hardware description language (HDL) suitable for implementation on an FPGA. To evaluate the suggested IGBT hardware model and the nonlinear circuit simulation technique, a chopper circuit is replicated, and an FPGA-in-the-loop simulation is carried out to compare the efficacy and accuracy of the model with both offline simulation results and real-time simulation results using MATLAB Simulink software and the Altera FPGA Cyclone IV GX development board.

Design and Implementation of a Multiplier free FPGA based OFDM Transmitter

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-carrier technique.The core operation in the OFDM systems is the FFT/IFFT unit that requires a large amount of hardware resources and processing delay. The developments in implementation techniques likes Field Programmable Gate Array (FPGA) technologies have made OFDM a feasible option. The goal of this paper is to design and implement an OFDM transmitter based on Altera FPGA using Quartus software. The proposed transmitter is carried out to simplify the Fourier transform calculation by using decoder instead of multipliers. After programming ALTERA DE2 FPGA kit with implemented project, several practical tests have been done starting from monitoring all the results of the implemented blocks (VHDL code) and compare them with corresponding results from simulation system implemented in matlab 2010a. The results of these practical tests show that the suggested approach gives a significant improvement in reducing complexity and processing delays (45 nsec) in comparison with the conventional implementations of OFDM transmitter.

A high frame-rate of cell-based histogram-oriented gradients human detector architecture implemented in field programmable gate arrays

In respect of the accuracy, one of the well-known techniques for human detection is the histogram-oriented gradients (HOG) method. Unfortunately, the HOG feature calculation is highly complex and computationally intensive. Thus, in this research, we aim to achieve a resource-efficient and low-power HOG hardware architecture while maintaining its high frame-rate performance for real-time processing. A hardware architecture for human detection in 2D images using simplified HOG algorithm was introduced in this paper. To increase the frame-rate, we simplify the HOG computation while maintaining the detection quality. In the hardware architecture, we design a cell-based processing method instead of a window-based method. Moreover, 64 parallel and pipeline architectures were used to increase the processing speed. Our pipeline architecture can significantly reduce memory bandwidth and avoid any external memory utilization. an altera field programmable gate arrays (FPGA) E2-115 was employed to evaluate the design. The evaluation results show that our design achieves performance up to 86.51 frame rate per second (Fps) with a relatively low operating frequency (27 MHz). It consumes 48,360 logic elements (LEs) and 4,363 registers. The performance test results reveal that the proposed solution exhibits a trade-off between Fps, clock frequency, the use of registers, and Fps-to-clock ratio.

An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters

An arc fault is an unintentional power discharge which may cause unexpected serious consequences such as fires. Under different voltage, current and loading conditions, along with unplanned locations, the occurrence times of arc faults are always random. Due to the randomness characteristic of arc fault, the measurement of the position and intensity of arc faults in real- time is a challenge to researchers. This brief proposes an analog- digital mixed-signal system applied to the arc fault detection in smart meters. The introduced digital system can automatically identify the load types and the filters of the reconfigurable analog circuit arranged according to the loads. The proposed digital system also implements the arc faults detecting threshold and its respective methods. A field-programmable analog array (FPAA) incorporates the involved analog functions, and an Altera Field Programmable Gate Array (FPGA) realizes the digital system. We test the performance of the proposed mixed-signal system under different load conditions with daily household appliances. The results show that the circuit is able to detect 99.6% of the arc faults during the experiment. The proposed mixed system provides a cost-effective package solution for accurately detecting the arc fault in modern smart meters.

An adjustable gain three port converter for battery and grid integration in remote location microgrid systems

The battery-grid integration (BGI) is the crux of microgrid systems that not only performs the energy management but also coordinates distributed energy resources and loads. The prevailing BGIs are either individual power converters based, which cause low efficiency and high cost, or multiport converter (MPC) based, which involve a higher component count and/or the lower voltage limit restriction in the DC port. With the increased penetration of distributed energy resources, the demand for MPCs with a wider buck-boost voltage gain capability is unavoidable. They can be used to interface low voltage sources like fuel cells, photovoltaic panels, batteries, etc. To perform the basic functionalities in BGI converters, like the power transfer from the storage to the grid and vice versa at different working conditions, the bidirectional capability in DC and AC ports is mandatory. This paper proposes a high voltage gain, bidirectional buck-boost port based hybrid MPC, called as an energy cushion multiport converter (ECMPC), for the integration of batteries with the single-phase AC microgrid (SPACMG). The ECMPC has three ports, among them one is the bidirectional AC port for the grid, the second one is the bidirectional DC port for the battery, and the last one is a DC output port for the common usage. The modes of operation with an appropriate switching sequence is detailed and a control scheme is also suggested. The performed comprehensive simulation analysis guides the component selection and the design of the converter. The critical comparison of the suggested converter with the prevailing single-phase bidirectional DC-AC converters being employed in the BGI is also presented. The theoretical study is supported by a laboratory corroboration. The system is managed for a minimal energy wastage through anew suggested minimal wastage energy management system (MWEMS). The system in the entirety is implemented and controlled by an ALTERA field-programmable gate array, ALTERA QUARTUS II 12.0SP2 processor.

FPGA-Based Hybrid Stepper Motor Drive System Design by Variable Structure Control

A stepper motor is usually operated in position open-loop control for simplicity. However, in order to improve the transient and steady-state performances of the stepper motor-based drive system, a high performance stepper motor drive system is usually designed to feed the encoder signal back to form a closed-loop system such as a general servo motor drive, and high-performance position and speed loop controller can then be used to overcome the nonlinear characteristics of the motor, such as the cogging force and impacts from external load. On the other hand, the existed cogging force of the hybrid stepper motor must be solved to increase the positioning precision. The variable structure control (VSC) is insensitive to the bounded uncertainty and load disturbance, and has been known as a high-performance controller. A predefined sliding surface is used to shape the system performances, and incorporate with switching control to achieve the robustness property. Thus, we applied the VSC to implement the stepper motor drive system about the position and speed control, and the switching control is used to overcome the cogging force. The field programmable gate array (FPGA) is a good alternative to be used to realize a motor drive system by considering its programmable ability and diverse designing environment. It is easily developed as an intellectual property (IP) for future use or combined as a part of a large control system. This paper showed the procedures to develop the hardware circuits for the variable structure controller, and applied it to stepper motor position and velocity control. Functions such as PI controllers, dq-axis transformation and two-phase space vector space vector modulation (SVPWM) designed for the stepper motor drives are also shown in the paper. The system simulation and hardware circuit realization are based on MATLAB/Simulink, and realized on Altera FPGA. Simulations on MATLAB/Simulink with trapezoidal velocity profile command, and experiments with and without the load added are shown to demonstrate the hardware performances and correctness.

Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA

This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.

Harmonic minimization of a single-phase asymmetrical TCHB multilevel inverter based on nearest level control method

Multilevel inverters are gaining special interest among researchers and in the industry due to their widespread applications and numerous merits. Obtaining high quality, more reliable output while using a reduced number of electronic components is the main purpose of most of the research conducted in this area of study. The purpose of this study is to apply the nearest level control (NLC) method to a 13-level transistor-clamped H-bridge (TCHB) inverter with unequal DC voltage supplies. The NLC method operates at the fundamental frequency, thus reducing switching losses, and can reduce the harmonic content significantly. The adopted multilevel inverter consists of two TCHB cells supplied with two asymmetrical DC input sources with a voltage ratio of 1:2. This structure reduces the number of electronic components, and the asymmetry in the DC input voltages results in a higher number of levels. The adopted topology and its proposed control method were simulated in Matlab/Simulink, and the simulation results were verified through experiments using an Altera field-programmable gate array (FPGA) board. The results showed that the topology and its control method are efficient in obtaining a high-quality output with an improved total harmonic distortion (THD).

RETRACTED ARTICLE: FPGA based peripheral myopathy monitoring using MFCV at dynamic contractions

This article describes the design of a wearable, remote inserted framework for the Peripheral Myopathy (PM) estimation in customary dynamic movements. This unique circumstance, the electromyographic investigation can give data about the muscle and nerve condition by evaluating the connected MFCV. The framework works with synchronized and digitized information tests from four electromyographic channels, which are situated on both hands of the individual test, misusing the rules given by an inserted positional filtering calculation. This work displays a novel approach for the assessment of MFCV that relies upon the excellent anode relative estimation standard. The system uses dynamic bitstream change of Electromyographic signs and low computational retort for utilization of bit stream cross-correlation. The structure totally chips away at Cyclone-V altera field programmable gate array. The test outcomes on five subjects (Human Beings) show the limit of the proposed procedure for planning the physiological muscle fibre conduction velocity values, as nitty–gritty in a therapeutic composition. In explicit, differentiating the remedial characteristics, obtained in controlled conditions, with the system evacuated muscle fibre conduction velocity, the proportionate preliminary conditions: preeminent bungle is, overall, 0.3 m/s. The framework restores a likelihood of invalid constant measures underneath of 2% (assuming the worst possible scenario).

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

Least Mean Squares Filters Suppressing the Radio-Frequency Interference in AERA Cosmic Ray Radio Detection

The production of radio waves from extensive air showers (EASs), initiated by ultra-high-energy cosmic rays, has been attributed to geomagnetic emission and charge excess processes. These days, the radio detection technique is used in many experiments aimed at studying EAS. One of them is the Auger Engineering Radio Array (AERA), located within the Pierre Auger Observatory. The frequency band observed by AERA radio stations is 30–80 MHz. The investigated frequency range is often very contaminated by human-made and narrowband radio-frequency interference (RFI). Suppression of these contaminations is crucial to lowering the rate of spurious triggers. An adaptive filter based on the least mean squares (LMS) algorithm can be an alternative one for currently used infinite impulse response (IIR)-notch nonadaptive filters. Measurements show that the LMS filter is very efficient in suppressing RFI and only slightly distorts radio signals. This article presents the 32-stage filters based on a transposed finite impulse response (FIR) filter implemented into cost-effective CycloneIV and CycloneV Altera field-programmable gate arrays (FPGAs) with a sufficient safety margin of the timing performance for the global clock above 200 MHz to obey the Nyquist requirement.

Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit

DOI: 10.26650/electrica.2019.18052 Arithmetic Logic Unit (ALU) is the essential part of the Central Processing Unit (CPU) core which performs arithmetical operations such as addition, subtraction, division, multiplication etc., logical operations such as and, or, xor etc. and shift-rotate operations. The CPU performance is directly related to the performance of ALU. In this study, the 64-bit ALU has been designed by using the Very High Speed Integrated Circuits Hardware Description Language (VHDL) and Altera Field Programmable Gate Array (FPGA) families, synthesized and simulated with the help of Altera Quartus II (Intel, Santa Clara, CA, USA) v13.0sp1 and Modelsim-Altera v10.1d (Intel, Santa Clara, CA, USA) software. Many different studies are given about ALU Design and Implementation with the use of FPGA architecture and VHDL language. The difference of this study from recent studies is that the proposed design allows the processing of the signed numbers. Also, Conditional Sum Adder (COSA) is used in addition operation instead of Carry Ripple Adder (CRA) or Carry Look-ahead Adder (CLA) because of its benefit in fast addition and less propagation delay of Carry Chain. Cite this article as : Saglam Bedir N, Kacar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica 2019; 10.26650/electrica.2019.18052.

FPGA Implementation of a Novel Construction of Optical Zero-Correlation Zone Codes for OCDMA Systems

Abstract This paper proposes a novel method for constructing optical zero-correlation zone (OZCZ) codes based on the Mutually Orthogonal Complementary Sets (MOCS) matrix and the concatenation operation. The most important property of the obtained codes is that the periodic correlation function of the proposed codes is zero for the phase shifts within the zero-correlation zone. The procedure of construction is simple, flexible and offers increasing number of users M = 2 n + 1 \left( {M = {2^{n + 1}}} \right) . In the other hand, we have presented a fully reconfigurable hardware implementation based on very high description language of the proposed OZCZ codes for optical code-division multiple-access encoder system. The implementation is performed on an Altera field-programmable gate arrays device using ROM memory and an up counter. The simulation results have been found satisfactory and are in conformity with the theoretical observations.

Secure color image encryption algorithm based on chaotic signals and its FPGA realization

SummaryIn this paper, we designed a three‐dimensional chaotic system (3D chaotic system). The continuous‐time chaotic system had already been transformed into discrete‐time (DT) chaotic system by Euler method. The phase portrait of DT chaotic system had been implemented on an oscilloscope via Altera field programmable gate array (FPGA) DE2‐115. A cryptographic system of RGB image security for 3D chaotic system was proposed. There are three features in the encryption system. First, we use the information of plaintext image to produce the initial conditions of chaotic system. Second, the image of the permutation process shuffles the position of pixels in the plaintext image among RGB channels separately. Third, in the diffusion process, the pixels information in the shuffled image had been concealed by the XOR operation. The 3D chaotic encryption system had been also implemented on Altera DE2‐115. Then, the cipher image can be obtained through the FPGA and simulated the image by Matlab code. In the security analysis, such as histogram analysis, correlation coefficient analysis, information entropy analysis, differential attack analysis (NPCR and UACI) have been performed in this paper. Experimental results show that the proposed algorithm has better security in comparison with other algorithms.

RETRACTED: An optimized reconfigurable algorithm for FPGA architecture oriented IoT applications

Application Specific Integrated Circuit (ASIC) can facilitate the user with high speed, but a small modification in the algorithm and architecture will lead to more cost in terms of design and development. In contrast Field Programmable Gate Array (FPGA) provides near optimal speed with reconfigurability of algorithm/architecture at any time. From research survey, we come to conclusion that Fast Fourier Transform (FFT) plays critical role in many applications such as Orthogonal Frequency Division Multiplexing (OFDM), image processing application and signal processing application. In this paper, we have developed a reconfigurable FPGA architecture for FFT algorithm. Also, reconfigurable algorithm is proposed to handover the reconfiguration control, so that the datapath can be changed. The proposed reconfigurable FPGA architecture is developed using Verilog and targeted in Altera FPGA boards. The evaluation and comparison of the proposed architecture shows remarkable improvement in terms of throughput, area and power.

On the Evaluation of Different High-Performance Computing Platforms for Hyperspectral Imaging: An OpenCL-Based Approach

Hyperspectral imaging systems are a powerful tool for obtaining surface information in many different spectral channels that can be used in many different applications. Nevertheless, the huge amount of information provided by hyperspectral images also has a downside, since it has to be processed and analyzed. For such purpose, parallel hardware devices, such as field-programmable gate arrays (FPGAs) and graphic processing units (GPUs), are typically used, especially for hyperspectral imaging applications under real-time constraints. However, developing hardware applications typically requires expertise in the specific targeted device, as well as in the tools and methodologies that can be used to perform the implementation of the desired algorithms in that device. In this scenario, the Open Computing Language (OpenCL) emerges as a very interesting solution in which a single high-level language can be used to efficiently develop applications in multiple and different hardware devices. In this work, the parallel Fast Algorithm for Linearly Unmixing Hyperspectral Images (pFUN) has been implemented in two different NVIDIA GPUs, the GeForce GTX 980 and the Tesla K40c, using OpenCL. The obtained results are compared with the results provided by the previously developed NVIDIA CUDA implementation of the pFUN algorithm for the same GPU devices for comparing the efficiency of OpenCL against a more specific synthesis design language for the targeted hardware devices, such as CUDA is for NVIDIA GPUs. Moreover, the FUN algorithm has also been implemented into a Bitware Stratix V Altera FPGA, using OpenCL, for comparing the results that can be obtained using OpenCL when targeting different devices and architectures. The obtained results demonstrate the suitability of the followed methodology in the sense that it allows the achievement of efficient FPGA and GPU implementations able to cope with the stringent requirements imposed by hyperspectral imaging systems.

A high speed photon counter system for microwave mercury ion frequency standard

This report describes a high speed photon counter system for microwave mercury ion frequency standard based on a field programmable gate array (FPGA). A high speed comparator is chosen to convert analog signal to digital pulse. A circuit with low-voltage differential signaling (LVDS) receiver in FPGA is used to capture the rising edges of the pulses. In our experiment, the clock of the Altera FPGA EP4CE10E22C8N is 80 MHz which is easy for logic design, and the de-serialization factor of the LVDS receiver is 8, the measured minimum pulse width that can be correctly captured is about 1.67 ns. As a compact and low-cost module, the photon counter system is used for the microwave mercury ion frequency standard.

FPGA implementation of fractional-order chaotic systems

This paper presents the digital implementation of fractional-order (FO) chaotic systems on Field Programmable Gate Array (FPGA). In the proposed work Simulink model of each chaotic system is first realized using HDL coder of MATLAB, wherein each coefficient and signal is represented using a fixed number of bits. The construced design is translated into VHDL code using hardware generation block. This code is further translated into bitstream file using Quartus software. The chaotic system is implemented by downloading the obtained bitstream file into Altera FPGA Cyclone IV E (EP4CE11529C7N) chip. A methodology has been developed to construct FO chaotic system using HDL coder. Five different FO chaotic systems, viz., Lorenz, Chen, Lü, Arneodo, and Lorenz Hyperchaotic system have been presented in the paper to illustrate the methodology. The systems have been implemented on FPGA platform. Analysis of each chaotic system is carried out on the basis of hardware resource utilization, static power analysis and synthesis frequency on FPGA. The results show that FPGA provides high-speed realizations with the desired accuracy and low power consumption for FO chaotic systems.

The Application of FPGA Based Real-Time Processing ESN in Pattern Recognition and Waveform Generation

In this paper, a real-time hardware-based Field Programmable Gate Array (FPGA) architecture Echo state network (ESN) of recurrent neural network (RNN), which real-timely gets the output weights of Reservoir Computing (RC) in FPGA, was used for pattern recognition and waveform generation. It is designed in strict accordance with the RC theory. The four parts of RC, which is input layer, reservoir layer, output layer, and weight training block, were all built in FPGA. The training of the RC was finished in real-time. We have verified its performance through implemented and verification in Altera FPGA. Experimental results showed that the real-time hardware RC can remember the ratio and recognize different period after it was trained as it was trained.