AlN Spacer Research Articles

Simulation-based optimization of barrier and spacer layers in InAlN/GaN HEMTs for improved 2DEG density

In this study, we utilize Nextnano device simulation software to systematically investigate the dependence of 2-DEG (two-dimensional electron gas) density on the barrier and spacer Layers in InAlN/GaN high electron mobility transistors (HEMTs). By simulating a range of barrier thicknesses, In mole fractions, and spacer layer thicknesses, we reveal the intricate ways in which these parameters influence device performance. Our simulations demonstrate that precise control of the InAlN barrier thickness and In mole fraction, along with the AlN spacer thickness, is crucial for optimizing 2DEG density and, consequently, the overall electrical properties of the HEMTs. Notably, our results highlight that an InAlN barrier thickness below 12 nm, coupled with an optimized In mole fraction and a finely tuned AlN spacer thickness close to 1 nm, significantly enhances 2DEG density without compromising mobility. These insights provide a detailed understanding of the material and structural dependencies critical for the design and development of high-performance InAlN/GaN HEMTs. Our study includes detailed calculations of the device's I–V characteristics. Notably, the highest peak output current is observed at a 1 nm AlN spacer thickness, reaching 0.91 A/mm. Our findings highlight a noteworthy agreement between the results derived from our computational simulations and experimental measurements.

Vacancy-type defects in AlInN/AlN/GaN structures probed by monoenergetic positron beam

Vacancy-type defects in AlInN(10 nm)/AlN(1–2 nm)/GaN were probed by using a positron annihilation technique. The crystal quality of the AlInN layer and atomic diffusion near heterointerfaces were also studied by x-ray diffraction reciprocal space mapping, transmission electron microscopy, and energy-dispersive x-ray spectroscopy. For an as-deposited sample without an AlN spacer layer (AlInN/GaN), Ga atoms diffused into the AlInN layer, and as a result, the concentration of Ga-vacancy-type defects in the GaN layer increased. The vacancy concentration was decreased by inserting the AlN layer, which was attributed to the suppression of out-diffusion of Ga from the GaN layer. The effect of the thickness of the AlN layer on the mobility of two-dimensional electron gas is discussed in terms of the introduction of vacancies into the channel region. The annealing behaviors of vacancies in the GaN layer and atomic exchange near heterointerfaces are also discussed.

Investigation of DC and RF characteristics of spacer layer thickness engineered recessed gate and field‐plated III‐nitride nano‐HEMT on β‐Ga2O3 substrate

AbstractIn this work, a field plated recessed gate III‐nitride HEMT on β‐Ga2O3 substrate is proposed using AlN spacer between AlGaN and GaN layers. The two‐dimensional electron gas (2DEG) transport characteristics, input/output, and RF characteristics of the proposed HEMT with AlN spacer layer of different thickness (1, 2, 3, 4, and 5 nm) are numerically simulated and compared with HEMT without spacer layer. The 2DEG, which is created at the junction of AlGaN/GaN, plays a crucial role in the operation of GaN HEMTs. With the help of AlN as spacer layer between AlGaN and GaN, an augmented 2DEG concentration is accomplished owing to its large conduction band offset, high polarization effect, and higher barrier. Additionally, the inclusion of AlN spacer layer shifts the 2DEG density away from interface, resulting minimized interface scattering which results into greater mobility. The HEMT exhibited a mobility of 1261 cm2/Vs, threshold voltage of −0.45 V, drain current of 1.12 A/mm, breakdown voltage of 149 V, and excellent RF characteristics, that is, cut‐off frequency (maximum oscillation frequency) of 384 GHz (546 GHz) using 2‐nm AlN spacer layer. The proposed III‐nitride HEMT on β‐Ga2O3 substrate with 2‐nm AlN spacer can be used for RF/microwave and high‐power nanoelectronics applications.

Investigation of performance enhancement of a recessed gate field-plated AlGaN/AlN/GaN nano-HEMT on β-Ga2O3 substrate with variation of AlN spacer layer thickness

Investigation of performance enhancement of a recessed gate field-plated AlGaN/AlN/GaN nano-HEMT on β-Ga2O3 substrate with variation of AlN spacer layer thickness

Theoretical Prediction of Mobility Improvement in GaN-Based HEMTs at High Carrier Densities

In this article, we use a semiclassical low-field mobility modeling framework, which includes all relevant scattering mechanisms, to examine the dependence of electron mobility on 2-D electron gas (2DEG) density in previously characterized high Al-content AlGaN/gallium nitride (GaN) high electron mobility transistors (HEMTs) with and without an AlN spacer layer. Polar optical phonon (POP) scattering has previously been identified as the dominant scattering mechanism in GaN-based HEMTs at room temperature, so the analysis of POP scattering rates is of particular importance. We find that the POP-limited mobility in both structures decreases with increasing 2DEG density up to a critical density of around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10}^{{13}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{2}}$ </tex-math></inline-formula> , above which we observe a significant improvement of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${46}\%$ </tex-math></inline-formula> , contrary to the behavior typically reported for GaN HEMT structures. The POP-limited mobility increase is explained by the interplay of ground-state energy and quasi-Fermi energy within the channel, by which intrasubband POP emission within the ground state is suppressed at high 2DEG densities. This provides a universal guideline for the design and operation of GaN-based HEMTs to achieve a minimum ON-resistance in switching applications at room temperature and above.

Characterization of AlInN/GaN based HEMT for Radio Frequency Applications

Background: The Si- and GaAs-based devices are not suitable for very high-speed and high-power applications. Therefore, GaN-based devices have emerged as a potential contender. Further improvement in the device characteristics using appropriate mole fractions of Al and InN in the barrier layer of AlInN has become inevitable. Objective: To design AlInN/GaN HEMT and present its salient features. Methods: The design method for the proposed AlInN/GaN HEMT includes a selection of materials, optimization of mole fraction in AlInN barrier layer, optimization of gate oxide thickness, optimization of device dimensions, and doping concentration. The fabrication steps necessary for the AlInN/GaN HEMT are also explained in the paper. Analysis of the structure has been carried out using the Silvaco TCAD tool. Results: All the obtained results have revealed that the proposed device can operate up to the cut-off frequency of 102 GHz and a maximum oscillation frequency of 230 GHz, which are suitable for radiofrequency applications. The minimum noise figure and maximum transducer power gain (~18 dB) achieved by the proposed device is quite acceptable. Conclusion: The use of the AlN spacer layer has improved the AlInN film quality and mitigates strain at the heterointerface. Moreover, it reduces the Coulomb attraction between ions in the supply layer and electrons in the channel layer thereby improving carrier mobility. Usage of a SiO2 layer between the gate and AlInN barrier layer has decreased the gate leakage current. This has reduced the subthreshold slope and increased ON/OFF current ratio (~1010). The proposed Si3N4 passivated HEMT offers a breakdown voltage of ~1395 V.

The Atomic Layer Etching Technique with Surface Treatment Function for InAlN/GaN Heterostructure

This paper studied an atomic layer etching (ALE) technique with a surface treatment function for InAlN/GaN heterostructures with AlN spacer layers. Various parameters were attempted, and 30 s O2 + 15 W BCl3 was chosen as the optimal recipe. The optimal ALE approach exhibited satisfactory etching results, with regard to the etch-stop effect, compared with other techniques. The atomic force microscopy (AFM) results showed an etching per cycle (EPC) value of 0.15 nm/cycle, with a 0.996 fit coefficient and root mean square (RMS) surface roughness of around 0.61 nm (0.71 nm for as-grown sample), which was the lowest in comparison with digital etching (0.69 nm), Cl2/BCl3 continuous etching (0.91 nm) and BCl3 continuous etching (0.89 nm). X-ray photoelectron spectroscopy (XPS) and scanning transmission electron microscopy with energy dispersive X-ray spectroscopy measurements (STEM/EDS) verified the indium clustered phenomena at the bottom apex of V-pit defects in the epi structure of InAlN/GaN high electron mobility transistors (HEMTs) for the first time, in addition to the surface morphology optimization for the ALE under-etching technique used in this work. The resistor hall effect (Hall) and AFM measurements demonstrated that after 4 or 5 ALE cycles, the two-dimensional electron gas (2-DEG) density and RMS roughness were improved by 15% and 11.4%, respectively, while the sheet resistance (Rsh) was reduced by 6.7%, suggesting a good surface treatment function. These findings were important for realizing high-performance InAlN/GaN HEMTs.

A comprehensive analysis of AlN spacer and AlGaN n-doping effects on the 2DEG resistance in AlGaN/AlN/GaN heterostructures

In this paper, several epitaxial variations influencing the two-dimensional electron gas (2DEG) in AlGaN/AlN/GaN heterostructures are investigated. The effects of an n-doped AlGaN barrier and of the AlN spacer thickness are studied by examining the sheet electron density (ns) and the mobility (µs) of the 2DEG using ID(VG) and C(VG) measurements, and 1D Schrödinger-Poisson (1DSP) simulations. Specifically, the correlations between the resistance, µs, ns and the polarization interface charges (σ) are studied. Besides the well-reported benefits of the AlN spacer on ns, we show that a thicker AlN spacer leads to larger ns due to the enhancement of the AlN polarization. In addition, we prove experimentally that an n-doped AlGaN barrier does not significantly improve the 2DEG density but leads to the formation of a second channel in the AlGaN barrier for negative gate voltage (VG ≤ 0 V), driving the overall improvement of the resistance.

Influence of AlN spacer and GaN cap layer in GaN heterostructure for RF HEMT applications

The influence of GaN cap layer and AlN spacer layer on mobility, carrier concentration, bandgap, crystal structure, inherent strain and stress is investigated for three widely used GaN heterostructure viz. Al0.3Ga0.7N/GaN, Al0.3Ga0.7N/AlN/GaN and GaN/Al0.3Ga0.7N/AlN/GaN on 6H-SiC substrate. The growth process is kept identical with less than 1% standard deviation for all three samples in order to investigate the true effect of GaN cap and AlN spacer layers on heterostructure properties. The GaN heterostructure properties have been extensively studied by Hall measurement, high-resolution x-ray diffraction, Raman and photoluminescence spectroscopy. The interdependency among structural, mechanical, electrical and optical properties of GaN heterostructure due to incorporation of AlN space and GaN cap layer is established. Furthermore, presented characterization results for all three heterostructures are identical with semiconductor device physics-based simulation. The carrier mobility and concentration were found least in conventional AlGaN/GaN heterostructure. It has been observed a pronounced increase of inherent tensile stress and carrier concentration by introducing AlN spacer layer between AlGaN and GaN, whereas carrier mobility increased by employing GaN cap layer on the top of the heterostructure.

Influence of AlN/GaN interfacial non-idealities on the properties of two-dimensional electron gas in AlGaN/AlN/GaN heterostructures

The influence of two types of AlN/GaN interfacial non-idealities, namely unintentional Ga incorporation into AlN spacer and blurring of the spacer due to Al and/or Ga atomic diffusion on the mobility and density of two-dimensional electron gas in AlGaN/AlN/GaN heterostructure was studied theoretically. It was found that moderate amount of GaN in the nominal AlN spacer does not affect much the mobility and density of 2DEG as long as the interface is abrupt. In contrast, the blurring of AlN/GaN interface was found to have a significant impact on the mobility and sheet resistance of the structure since the GaN channel actually becomes AlGaN and alloy-disorder scattering takes place.

High conductivity InAlN/GaN multi-channel two-dimensional electron gases

In this study, we propose a novel, high-conductivity multi-channel heterostructure based on lattice-matched InAlN/GaN channels with modulation-doping-induced two-dimensional electron gases (2DEGs). To facilitate device processing, the channel period thickness was minimized while maintaining a high electron mobility in each channel. We demonstrate a 10-channel heterostructure with a period thickness of 14 nm and a total sheet resistance of 82 Ω □−1. By increasing the doping concentration in each channel, much higher carrier densities per channel were achieved, resulting in an ultra-low sheet resistance of 36 Ω □−1. Furthermore, optimizing the heterostructure design enabled high electron mobilities, up to 1530 cm2 V−1 s−1, independent of the number of channels, by secluding the 2DEG from the barrier interfaces in each channel to avoid both strong interface roughness and ionized impurity scattering. This was achieved by modulation-doping of the GaN channel and the insertion of a GaN interlayer between the InAlN barrier and the AlN spacer. This approach offers a new platform for designing high conductivity heterostructures, where the general trade-off between electron mobility and carrier density can be significantly alleviated.

Low-sheet-resistance high-electron-mobility transistor structures with strain-controlled high-Al-composition AlGaN barrier grown by MOVPE

We demonstrated low-sheet-resistance AlGaN high electron mobility transistors (HEMTs) using a strain-controlled high-Al-composition AlGaN barrier grown by MOVPE. We systematically investigated the effects of the AlGaN-barrier’s growth conditions on the electrical characteristics. We found that growing an AlGaN barrier with nitrogen as a carrier gas increases dislocation density in the AlGaN barrier, resulting in reduction of strain in the AlGaN barrier and the top of the GaN channel. Reduction strain in the GaN channel can improve electron mobility. Moreover, dislocation and impurity scattering are prevented using an AlN spacer. Finally, we achieved low-sheet-resistance HEMT structures with a high Al composition of over 0.60. The lowest sheet resistance is 211 Ω/sq. with electron mobility of 1820 cm2 V−1 s−1 using an Al0.68Ga0.32N barrier.

Fabrication and pH-Sensitivity Analysis of MOS-HEMT Dimensional Variants for Bio-Sensing Applications.

This work reports the fabrication, characterization and testing for pH sensitivity of dielectric modulated MOS-HEMT(Metal oxide semiconductor- high electron mobility transistor) devices for bio-sensing applications. The primary aim here is to develop high sensing devices for bio-detections. The oxide based gate area is used in ensuring the device performance through pH detection done prior to packaging and metal probing. Device parameters; gate length LG, gate width WG, gate spacing from source-drain ends, LSG and LGD have been varied to investigate the effect on pH sensitivity. The HEMT stack with AlN spacer has been grown through MOCVD (Metal-Organic Chemical Vapor Deposition) technique with no intentional doping on Si (silicon) substrate. Commercial buffer samples for pH values of 4, 7, 9.2 have been used to test the devices using drop casting technique. Drain current (ID) based sensitivity analysis shows that the device having ( [Formula: see text], [Formula: see text] and [Formula: see text]) exhibits a maximum sensitivity of 3.361 mA/pH. The devices exhibit exemplary performance when device dimensions meet the following constraints i.e. LSG: minimum, LG: moderate and LGD > 2*LSG. Average sensitivities attained is in the range 1.69 mA/pH for a device with [Formula: see text], [Formula: see text] and [Formula: see text].

Mass production-ready characteristics of AlGaN/AlN/GaN high-electron-mobility transistor structures grown on 200 mm diameter silicon substrates using metal-organic chemical vapor deposition

Mass production-ready technologies of AlGaN/AlN/GaN high-electron-mobility transistor (HEMT) structures on 200 mm diameter silicon substrates are developed using a large-scale metal-organic chemical vapor deposition system. High-yield epitaxial substrates on large-diameter wafers are required for reducing the cost of industrializing power device applications. Through multi-point vertical leakage current measurements, it was confirmed that the AlGaN/AlN/GaN HEMT, under optimum growth conditions, showed high yield characteristics such as a highly uniform leakage current and a low number of breaking points over the entire 200 mm diameter wafer. On introducing an AlN spacer layer between the AlGaN Schottky barrier and the GaN channel, a lower on-state resistance for power devices can be expected. Cross-sectional transmission electron microscopy images revealed that the thin AlN spacer layer was grown between the AlGaN and GaN layers with atomically abrupt and flat interfaces. HEMT structures with an AlN spacer layer exhibited a considerably high two-dimensional-electron-gas mobility of 2000 cm2 V−1 s−1 at room temperature and 10 700 cm2 V−1 s−1 at 77 K. The AlN spacer layer between the AlGaN and GaN layers was successfully fabricated and suppressed the alloy disorder scattering effect.

Ultrawide bandgap AlxGa1–xN channel heterostructure field transistors with drain currents exceeding 1.3 A mm−1

We report an Ultrawide Bandgap Al0.4Ga0.6N channel metal-oxide-semiconductor heterostructure field effect transistor with drain currents exceeding 1.33 A mm−1 (pulse) and 1.17 A mm−1 (DC), around a 2-fold increase over past reports. This increase was achieved by incorporating a hybrid barrier layer consisting of an AlN spacer, n-doped Al0.6Ga0.4N barrier and a thin reverse graded AlxGa1–xN (x from 0.60 to 0.30) cap layer. To enhance current spreading, a “perforated” channel layout comprising of narrow channel sections separated by current blocking islands was used. A composite ALD deposited ZrO2/Al2O3 film was used as gate dielectric. A breakdown field above 2 MV cm−1 was measured.

Material investigations for improving stability of Au free Ta/Al-based ohmic contacts annealed at low temperature for AlGaN/GaN heterostructures

Gold-free Ta/Al-based ohmic contacts fabricated by sputtering on AlGaN/GaN heterostructures and annealed at low temperature were investigated. The presence of a thin AlN spacer layer at the AlGaN/GaN heterojunction is demonstrated to prevent the ohmic contact formation as shown by rectifying behavior after annealing. Ta as an additional capping layer on Al leads to a severe morphology degradation and subsequent deterioration of the metal stack after annealing at 600 °C due to strong Ta–Al alloying verified by transmission electron microscopy. Using the compound metal TiN as capping layer circumvents the alloy formation, thereby making the contacts much more stable under annealing. A low contact resistance of 0.8 Ω mm was obtained using Ta/Al/TiN metal layers annealed at only 500 °C. The nature of the current transport was investigated by analyzing the temperature dependence of the specific contact resistance, which points towards a current path through the AlGaN barrier by thermionic field emission.

An ultra-sensitive AlGaN/AlN/GaN/AlGaN photodetector: Proposal and investigation

In this paper, an AlGaN/AlN/GaN/AlGaN photodetector high electron mobility transistor is designed and simulated. The proposed structure incorporates an AlN spacer layer between the AlGaN and GaN layers to ensure good control of the two-dimensional gas, which improve, in turn, the device controllability. Besides, an overall figures of merit assessment is performed to highlights the design benefits. The suggested device provides a very high responsivity of 0.2641 A/W, a photocurrent of 1.1 × 10−7 A, a suitable (Iilumination/Idark) rejection of 10.8, and a high efficiency η of about 77%. The photo and dark current is at 2 V, 87 mA and 8 mA, respectively. A subthreshold slope (SS) of 53 mV/V and 42 mV/V, and a transconductance gm of 260 ms/mm and 180 ms/mm are obtained. The proposed photodetector springly outperforms the HEMT PD designs previously proposed in the literature.

Oxygen-based digital etching of AlGaN/GaN structures with AlN as etch-stop layers

O2 plasma-based digital etching of Al0.25Ga0.75N with a 0.8 nm AlN spacer on GaN was investigated using an inductively coupled plasma etcher. Silicon oxide layer was used as the hard mask. At 40 W RF bias power and 40 sccm oxygen flow, the etch depth of Al0.25Ga0.75N was 5.7 nm per cycle. The 0.8 nm AlN spacer layer acted as an etch-stop layer in three cycles. The surface roughness improved from 0.66 to 0.33 nm after the three and seven digital etch cycles. Compared to the dry etch only approach, this technique smoothed the surface instead of causing surface roughening. Compared to the selective thermal oxidation with a wet etch approach, this method is less demanding on the epitaxial growth and saves the oxidation process. It was shown to be effective in precisely controlling the AlGaN etch depth required for recessed-AlGaN HEMTs.

Post-Annealing on the Ohmic Contact and Gate Recess Simultaneously in AlGaN/GaN MIS-Hemt

AlGaN/GaN HEMTs have been widely used in RF power amplifiers and power switching circuits. The primary reasons are because of high electron mobility and high breakdown electric field in GaN materials. Moreover, a 2DEG formed from polarization effects at the AlGaN/GaN heterojunction enables a low channel resistance and thus a low on-resistance. However, devices fabricated with the inherent 2DEG channel are depletion-mode FETs. For practical applications, it prefers an enhancement-mode (E-mode) device with the threshold voltage > 0 V. The common approaches to implement an E-mode device include gate recess, p-GaN layer, and F-ion treatment. The p-GaN layer used to deplete the channel underneath the gate at 0V and induce 2DEG with positive gate bias. But the gate swing voltage is limited due to the gate leakage current. The F-ion treatment under the gate has a reliability issue. The gate recess combined an insulator layer device (MIS-HEMT) is practical for E-mode operation to achieve the high gate voltage swing and low gate leakage current. However, the damage from gate recess and the relatively poor MOS interface between GaN and the insulators are problems to be overcome. Conventional E-mode MIS-HEMT fabrication starts with high-temperature annealing to ohmic contact then gate recess for gate metallization. Second annealing is required to reduce the gate recess damage. In this study, we did not anneal the device for ohmic contact first but anneal the device after the gate recess with suitable conditions to achieve a good ohmic contact and reduce recess damage. By the post-annealing on the ohmic contact and gate recess simultaneously, the interfacial density of state (Dit) of MIS in the E-mode MIS-HEMT was improved with low contact resistance. The epitaxial layers were grown by MOCVD including a ~3900-nm buffer layer, a 325-nm GaN channel layer, a 1-nm AlN spacer layer, a 21.5-nm Al0.25Ga0.75N barrier, and a 4.1-nm in-situ SiN cap layer. First, device isolation was implemented by ICP etching down to the buffer layer. The ohmic contact was made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) without annealing. Using ICP to perform gate recess, and then annealed by RTA at 875 °C in an N2 circumstance for 40 s. The gate dielectric SiN was deposited at 300 °C by PECVD, then annealed by RTA at 450 °C for 1 min in an N2 circumstance. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metal stack was used to form gate metal contact. Finally, the devices were passivated by a 200-nm SiN deposited by PECVD. The C-V and I-V characteristics of fabricated devices were measured by the Agilent B1500A and B1505A. The leakage current was reduced in the devices with proposed annealing. Double sweep C-V characteristics at 100-kHz of devices with proposed annealing step show a smaller hysteresis and lower flat band voltage shift than devices with traditional ohmic annealing. Moreover, the frequency dependent C-V measurements show that device with proposed annealing step effectively reduces the dispersion phenomenon. Conductivity method was applied to extract interface trap density as a commonly used analytical method for the III-V materials [3]. The calculated Dit of the device with proposed annealing step shows lower interface trap density than the device with traditional ohmic annealing. The calculated Dit was reduced from 7.1E12 to 4.8E12 eV-1cm-2. As a result, annealing after gate recess can really improve the interface quality and reduce the damage from dry etching, and form good ohmic contact without the extra annealing step. Figure 1

Influence of barrier and spacer layer on structural and electrical properties of AlGaN/GaN HEMT

A systematic numerical simulation of AlGaN/GaN-based HEMT is performed to demonstrate a strong dependence between the thickness and content of Al in the barrier layer on the electrical characteristics of HEMT. The impact of introducing a thin AlN spacer layer is also studied. A high mobility of 1901.2 cm2/Vs and an electron concentration of 3.036 × 1013 cm−2 is achieved by adding an AlN spacer in the standard AlGaN/GaN HEMT having barrier thickness as 27 nm and Al composition of 25%, while electron mobility and electron density of 1767 cm2/Vs and 2.778 × 1013 cm−2, respectively, is achieved for a standard optimized AlGaN/GaN structure. It is further presented that optimization of HEMT structure using numerical simulation tools is an efficient method of improving the electrical properties of the transistor structure preceding the fabrication of the device.